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31. 发明授权

US4200968A VMOS transistor and method of fabrication 失效
标题翻译： VMOS晶体管及其制造方法
公开(公告)号：US4200968A
公开(公告)日：1980-05-06
申请号：US932232
申请日：1978-08-09
申请人： James E. Schroeder
发明人： James E. Schroeder
IPC分类号： H01L21/306 , H01L29/08 , H01L29/423 , B01J17/00
CPC分类号： H01L29/0847 , H01L21/30608 , H01L29/4236 , Y10S148/025 , Y10S148/053 , Y10S148/145
摘要： A vertical insulated gate field effect transistor having a first first conductivity layer, a second second conductivity layer thereon, a third first conductivity layer thereon, a groove extending from the surface of the third layer through the second layer into the first layer, a layer of insulation and gate material in the groove and a shallow first conductivity vertical region extending from the third layer into the second layer along the groove to form a short channel in the second layer with a shallow device junction.The device is fabricated by masking the three semiconductor layers and etching the third layer and part of the second layer to form a groove, diffusing second conductivity impurities to a shallow depth in the groove, continue the etching to extend the groove through the second layer into the first layer. A layer of insulation and gate material are formed in the groove to produce the vertical channel.
摘要翻译：一种垂直绝缘栅场效应晶体管，具有第一第一导电层，其上的第二第二导电层，其上的第三第一导电层，从第三层的表面延伸穿过第二层到第一层的凹槽，绝缘和栅极材料以及沿着沟槽从第三层延伸到第二层的浅的第一导电垂直区域，以在具有浅的器件结的第二层中形成短沟道。该器件通过掩蔽三个半导体层并蚀刻第三层和第二层的一部分来形成沟槽，将第二导电杂质扩散到凹槽中的浅深度，继续蚀刻以将沟槽延伸穿过第二层，形成第一层。在沟槽中形成绝缘层和栅极材料层以产生垂直沟道。

32. 发明授权

US4198742A Method for the production of a solid electrolytic capacitor 失效
标题翻译：生产固体电解电容器的方法
公开(公告)号：US4198742A
公开(公告)日：1980-04-22
申请号：US904873
申请日：1978-05-11
申请人： Robert Ramer , Rudolf Soldner
发明人： Robert Ramer , Rudolf Soldner
IPC分类号： H01G9/00 , H01G9/012 , B01J17/00
CPC分类号： H01G9/012 , Y10T29/417
摘要： A solid electrolytic capacitor has an anode which consists of a sintered tantalum member having a dielectrically effective oxide layer located thereon and a counterelectrode consisting of semiconducting manganese dioxide. An anode wire is coated with polytetrafluorethylene in the vicinity of the point it enters the sintered member. In a method for producing such an electrolytic capacitor, the anode wire is brushed with a suspension containing the polytetrafluorethylene in a solvent in the vicinity of the wire entry point, before the manganese dioxide layer is produced, and the suspension is burnt-in for annealed after such application, where annealing occurs at a temperature of approximately 300.degree. C. over a period of time of approximately ten minutes.
摘要翻译：固体电解电容器具有阳极，其由具有位于其上的介电有效氧化物层的烧结钽构件和由半导体二氧化锰组成的反电极组成。阳极线在其进入烧结构件的点附近用聚四氟乙烯涂覆。在制造这样的电解电容器的方法中，在制造二氧化锰层之前，在引线入口点附近的溶剂中，将含有聚四氟乙烯的悬浮液刷过阳极线，并且将该悬浮体烧成退火在这种应用之后，在大约10分钟的时间内，在大约300℃的温度下进行退火。

33. 发明授权

US4193182A Passivated V-gate GaAs field-effect transistor and fabrication process therefor 失效
标题翻译：钝化的V栅极GaAs场效应晶体管及其制造工艺
公开(公告)号：US4193182A
公开(公告)日：1980-03-18
申请号：US883978
申请日：1978-03-06
申请人： Don H. Lee
发明人： Don H. Lee
IPC分类号： H01L21/265 , H01L29/10 , H01L29/423 , H01L29/812 , B01J17/00
CPC分类号： H01L29/1029 , H01L21/26546 , H01L29/42316 , H01L29/812
摘要： The specification describes a new and improved Schottky-gate field-effect transistor (FET) and process for fabricating same wherein selective and multiple ion implanatation doping steps are used to form source, drain and channel regions in a semiconductor body. The semiconductor body is then selectively etched to expose the source and drain regions previously formed, while leaving intact a mesa-shaped, high resistivity stabilizing region of the semiconductor body overlying and electrically stabilizing the ion-implanted channel region. The semiconductor body is then partially passivated with a chosen dielectric layer having two openings therein for exposing source and drain regions, respectively, and a third opening which is aligned with the channel region. Ohmic contacts are deposited in the source and drain openings, and thereafter a V-shaped groove is etched in the mesa-shaped region overlying the channel region to expose a very small area of the channel region. Schottky-gate metallization is then deposited in this V-shaped groove to form the Schottky-gate electrode of the device, and the fully passivated device thus formed exhibits excellent source and drain contact resistance and a minimum of drain-to-gate capacitance.
摘要翻译：本说明书描述了一种新的和改进的肖特基势垒场效应晶体管（FET）及其制造方法，其中使用选择性和多离子注入掺杂步骤在半导体体内形成源极，漏极和沟道区。然后选择性地蚀刻半导体体，以暴露预先形成的源区和漏区，同时保留半导体体的台状，高电阻率稳定区，覆盖并电离稳定离子注入沟道区。然后半导体本体被部分地钝化，其中分别具有两个开口的选择的电介质层以分别暴露出源区和漏区，以及与沟道区对准的第三开口。欧姆接触沉积在源极和漏极开口中，之后在覆盖沟道区的台面形区域中蚀刻V形槽，以暴露通道区域的非常小的区域。然后将肖特基金属化沉积在该V形沟槽中以形成器件的肖特基 - 栅电极，并且由此形成的完全钝化器件表现出优异的源极和漏极接触电阻以及最小的漏极 - 栅极电容。

34. 发明授权

US4188707A Semiconductor devices and method of manufacturing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US4188707A
公开(公告)日：1980-02-19
申请号：US814552
申请日：1977-07-11
申请人： Masaru Asano , Tetsushi Sakai , Yoshio Sunohara
发明人： Masaru Asano , Tetsushi Sakai , Yoshio Sunohara
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/288 , H01L21/331 , H01L21/768 , H01L23/532 , H01L29/41 , H01L29/43 , H01L29/45 , H01L29/73 , B01J17/00
CPC分类号： H01L21/768 , H01L21/28 , H01L23/53271 , H01L29/41 , H01L29/456 , H01L2924/0002 , Y10S148/018 , Y10S148/02 , Y10S148/124
摘要： The semiconductor device comprises a semiconductor substrate, a polycrystalline silicon semiconductor body extending upwardly from a portion of the surface of the semiconductor substrate and containing an impurity at a substantially uniform concentration, and a metal electrode disposed on the top surface of the polycrystalline silicon semiconductor body. The metal electrode extends in the lateral direction beyond the periphery of the top surface of the polycrystalline silicon semiconductor body.
摘要翻译：半导体器件包括半导体衬底，从半导体衬底的表面的一部分向上延伸并含有基本均匀浓度的杂质的多晶硅半导体器件和设置在多晶硅半导体本体的顶表面上的金属电极。金属电极在横向方向上延伸超过多晶硅半导体本体的顶表面的周边。

35. 发明授权

US4184192A Solid electrolyte compacitor using low resistivity metal oxide as cathode collector 失效
标题翻译：使用低电阻率金属氧化物作为阴极收集器的固体电解质电容器
公开(公告)号：US4184192A
公开(公告)日：1980-01-15
申请号：US877839
申请日：1978-02-15
申请人： Akihiko Yoshida , Atsushi Nishino
发明人： Akihiko Yoshida , Atsushi Nishino
IPC分类号： H01G9/00 , H01G9/042 , B01J17/00
CPC分类号： H01G9/0425 , Y10T29/417
摘要： A solid electrolyte capacitor which utilizes a semiconductive metal oxide such as manganese dioxide as solid electrolyte can be improved particularly in its dielectric loss and frequency-capacitance characteristics by the use of an oxide of Ru, Rh, Pd, Re, Os and/or Ir as a material of a cathode collector layer covering the solid electrolyte layer either in place of or together with colloidal carbon which is used commonly. It is preferable that a conductive layer formed on the cathode collector layer is a plasma-sprayed coating of a metal such as copper.
摘要翻译：利用诸如二氧化锰的半导体金属氧化物作为固体电解质的固体电解电容器可以通过使用Ru，Rh，Pd，Re，Os和/或Ir的氧化物在其介电损耗和频率 - 电容特性方面得到改善作为覆盖固体电解质层的阴极集电体层的材料，代替或与常用的胶体碳一起。优选地，形成在阴极集电体层上的导电层是诸如铜的金属的等离子体喷涂涂层。

36. 发明授权

US4182025A Manufacture of electroluminescent display devices 失效
标题翻译：电致发光显示装置的制造
公开(公告)号：US4182025A
公开(公告)日：1980-01-08
申请号：US837611
申请日：1977-09-28
申请人： Dennis K. Wickenden
发明人： Dennis K. Wickenden
IPC分类号： H01L21/762 , H01L25/075 , H01L27/15 , B01J17/00
CPC分类号： H01L27/156 , H01L21/76264 , H01L25/0753 , H01L21/76289 , H01L2224/48137 , H01L2224/49175 , H01L2924/0002
摘要： In the manufacture of a monolithic light-emitting diode array, electrical isolation between the n-type regions of portions of the array, for example the columns of a matrix array, is effected by mechanically cutting channels between the portions, through the n-type region and the common electrode. This method of forming the isolation channels makes it possible to produce much narrower channels than can be achieved by chemical etching, thus providing a high resolution array.
摘要翻译：在单片发光二极管阵列的制造中，阵列部分的n型区域（例如矩阵阵列的）之间的电隔离通过机械地切割部分之间的通道，通过n型区域和公共电极。形成隔离通道的这种方法使得可以产生比通过化学蚀刻可以实现的更窄的通道，从而提供高分辨率阵列。

37. 发明授权

US4179794A Process of manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的工艺
公开(公告)号：US4179794A
公开(公告)日：1979-12-25
申请号：US893275
申请日：1978-04-05
申请人： Masao Kosugi , Takashi Ogata
发明人： Masao Kosugi , Takashi Ogata
IPC分类号： H01L21/301 , H01L21/316 , H01L21/56 , H01L21/78 , H01L23/31 , H01L29/732 , H01L29/808 , H01L29/861 , B01J17/00
CPC分类号： H01L23/3178 , H01L21/31654 , H01L21/56 , H01L21/78 , H01L29/7325 , H01L29/8083 , H01L29/8613 , H01L2924/0002 , Y10S148/028
摘要： On a common semiconductor wafer constituted by a PN-lamination are formed a number of semiconductor device units. Recessed grooves are formed into this wafer by an etching technique at such sites as one corresponding to the boundaries of the respective adjacent semiconductor device units. To protect the PN-junctions of the wafer exposed on the etched grooves, these surfaces are coated with a thermo-setting resin. Thereafter, the semiconductor wafer is severed apart at the respective recessed grooves into respective individual chips of semiconductor devices.
摘要翻译：在由PN层压构成的公共半导体晶片上形成多个半导体器件单元。通过蚀刻技术在与相应的相邻半导体器件单元的边界相对应的位置处形成嵌入的凹槽。为了保护暴露在蚀刻槽上的晶片的PN结，这些表面涂有热固树脂。此后，将半导体晶片在各个凹槽处分开切割成半导体器件的各个芯片。

38. 发明授权

US4173821A Method of producing semiconductor devices 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US4173821A
公开(公告)日：1979-11-13
申请号：US827091
申请日：1977-08-23
申请人： Masatoshi Yamamoto , Keisuke Makino , Kiyomi Suzukawa , Souichirou Nakamura , Kiyomi Sakai
发明人： Masatoshi Yamamoto , Keisuke Makino , Kiyomi Suzukawa , Souichirou Nakamura , Kiyomi Sakai
IPC分类号： H01L23/48 , H01L21/50 , H01L21/56 , H01L21/60 , B01J17/00
CPC分类号： H01L24/86 , H01L21/56 , H01L24/29 , H01L24/75 , H01L24/83 , H01L2224/2919 , H01L2224/8319 , H01L2224/83801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , Y10T29/49004 , Y10T29/49121
摘要： In the process of fabrication of semiconductor devices, a lead frame hoop supplied from a supply reel is set forward to successively enter into a series of fabricating steps. After having been subjected to pellet bonding, wire bonding and resin-molding, it is wound up about a take-up reel. Baking step is performed with the lead frame hoop wound on the take-up reel. The lead frame hoop unwound from the take-up reel is cut into separate individual semiconductor device units from one another and the measurement of characteristics and the classification of the thus prepared units are carried out with the positions of the units maintained as they were at the cutting step. Accordingly, the process has a smaller number of steps and therefore the production cost is reduced, and the speed of working is improved.
摘要翻译：在制造半导体器件的过程中，从供带盘供给的引线框环向前设置以依次进入一系列制造步骤。在进行颗粒粘合，引线接合和树脂成型之后，将其卷绕在卷绕卷轴上。烘烤步骤是用引导框架缠绕在卷取卷轴上进行的。将从卷取卷轴展开的引导框架环彼此切割为独立的单独的半导体器件单元，并且由此将所准备的单元的特性和分类的测量结果按照它们在切割步骤因此，该方法具有较少的步骤数，因此降低了生产成本，并提高了加工速度。

39. 发明授权

US4173818A Method for fabricating transistor structures having very short effective channels 失效
标题翻译：制造具有非常短的有效通道的晶体管结构的方法
公开(公告)号：US4173818A
公开(公告)日：1979-11-13
申请号：US910254
申请日：1978-05-30
申请人： Ernest Bassous , Tak H. Ning , Carlton M. Osburn
发明人： Ernest Bassous , Tak H. Ning , Carlton M. Osburn
IPC分类号： H01L21/033 , H01L21/265 , H01L21/336 , H01L21/8247 , H01L29/10 , H01L29/78 , H01L29/788 , H01L29/792 , B01J17/00
CPC分类号： H01L29/7816 , H01L21/033 , H01L21/2652 , H01L29/1045 , H01L29/66659 , H01L29/66674 , H01L29/7801 , H01L29/7835
摘要： A method, including a sequence of process steps, for fabricating insulated gate field effect transistors having very short effective channel lengths. In a first version of the method, the source and drain regions of the device are opened in one process step and self-alignment of the source and the drain to the gate is achieved in one masking step. The drain region is then masked and the source side of the channel is implanted to adjust the threshold voltage of the high threshold voltage channel region. In a second version of the method, the source region is opened and self-aligned with the gate prior to the opening of drain region. Implantation to adjust the threshold voltage of the high threshold voltage channel region takes place before the drain region is opened, and then the drain region is opened and self-aligned with the gate in a further masking step. In either version, the threshold voltage is adjustable and the channel length is controlled to be a small value.
摘要翻译：一种包括一系列工艺步骤的方法，用于制造具有非常短的有效通道长度的绝缘栅场效应晶体管。在该方法的第一版本中，器件的源极和漏极区域在一个处理步骤中被打开，并且在一个掩模步骤中实现源极和漏极到栅极的自对准。然后对漏极区进行掩模，并且注入沟道的源极侧以调整高阈值电压沟道区的阈值电压。在该方法的第二版本中，源极区域在漏极区域打开之前被打开并与栅极自对准。在漏极区域打开之前进行用于调整高阈值电压沟道区域的阈值电压的植入，然后在另外的掩模步骤中，漏极区域被打开并与栅极自对准。在任一版本中，阈值电压是可调节的，并且通道长度被控制为小的值。

40. 发明授权

US4173064A Split gate electrode, self-aligned antiblooming structure and method of making same 失效
标题翻译：分离栅电极，自对准防结构及其制作方法
公开(公告)号：US4173064A
公开(公告)日：1979-11-06
申请号：US826279
申请日：1977-08-22
申请人： Stephen A. Farnow
发明人： Stephen A. Farnow
IPC分类号： H01L29/762 , H01L21/339 , H01L27/148 , B01J17/00
CPC分类号： H01L27/14887
摘要： Excess signal charge generated in response to optical overload of a charge-coupled sensing region is removed from that region by an antiblooming drain implanted in the substrate of the sensing array. The antiblooming drain is separated from the row of sensing regions by a potential barrier produced by a gate electrode associated with the drain. In fabricating the charge-coupled optical imager, the antiblooming drain is self-aligned with the antiblooming gate electrodes by first providing a pair of spaced-apart antiblooming gate electrodes and implanting the drain region into the substrate using the gate electrodes as a mask.
摘要翻译：响应于电荷耦合感测区域的光学过载而产生的过多的信号电荷通过植入感测阵列的衬底中的防引线漏极从该区域去除。通过由与漏极相关联的栅电极产生的势垒将防引流漏极与感测区的行分离。在制造电荷耦合光学成像仪时，通过首先提供一对隔开的抗折射栅极电极，并使用栅电极作为掩模将漏极区域注入到衬底中，使抗污染漏极与抗电晕栅电极自对准。

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