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31. 发明申请

US20080052558A1 SYSTEMS AND METHODS FOR REDUCED COMPLEXITY LDPC DECODING 有权
标题翻译：用于降低复杂度LDPC解码的系统和方法
公开(公告)号：US20080052558A1
公开(公告)日：2008-02-28
申请号：US11689357
申请日：2007-03-21
申请人： Guohui Sun , Jing Jin , Wenbin Yao , Hongwen Yang
发明人： Guohui Sun , Jing Jin , Wenbin Yao , Hongwen Yang
IPC分类号： G06F11/00
CPC分类号： H03M13/112 , H03M13/1105 , H03M13/1117 , H03M13/658 , H03M13/6583 , H04L1/005 , H04L1/0057
摘要： Systems and methods for generating check node updates in the decoding of low-density parity-check (LDPC) codes use new approximations in order to reduce the complexity of implementing a LDPC decoder, while maintaining accuracy. The new approximations approximate the standard sum-product algorithm (SPA), and can reduce the approximation error of min-sum algorithm (MSA) and have almost the same performance as sum-product algorithm (SPA) under both floating precision operation and fixed-point operation.
摘要翻译：在低密度奇偶校验（LDPC）码的解码中生成校验节点更新的系统和方法使用新的近似，以便在保持精确度的同时降低实现LDPC解码器的复杂度。新近似近似于标准求和积算法（SPA），并且可以减少最小和算法（MSA）的近似误差，并且在浮动精度运算和固定精度算法（SPA）下具有与sum-product算法（SPA）几乎相同的性能，点操作。

32. 发明申请

US20070245217A1 Low-density parity check decoding 审中-公开
标题翻译：低密度奇偶校验解码
公开(公告)号：US20070245217A1
公开(公告)日：2007-10-18
申请号：US11729846
申请日：2007-03-28
申请人： Stefano Valle
发明人： Stefano Valle
IPC分类号： H03M13/00
CPC分类号： H03M13/1125 , H03M13/1102 , H03M13/1117 , H03M13/112 , H03M13/1122 , H03M13/658 , H03M13/6583
摘要： Low Density Parity Check encoded signals propagated over a channel are decoded by iteratively producing messages representative of the a-posteriori probability of output decoded signals as a function of check-to-bit messages produced from bit-to-check messages via check-node update computation. The check-node update computation is performed as a MIN-SUM approximation and the reliability of the output messages from the check-node update computation is determined by the least reliable incoming message M(i). The decoding includes: identifying the smallest and second smallest modulus of bit-to-check messages, the signs of output messages and the position of a least reliable incoming message, and producing an updated version of the messages representative of the a-posteriori probability as a function of the smallest or the second smallest of i-th check-to-bit messages, the signs of said output messages and the position of said least reliable incoming message.
摘要翻译：低密度奇偶校验通过迭代地产生表示输出解码信号的后验概率的消息来解码通过信道传播的编码信号作为通过校验节点更新从位到检查消息产生的检查到位消息的函数来解码计算。执行校验节点更新计算作为MIN-SUM近似，并且由最不可靠的输入消息M（i）确定来自校验节点更新计算的输出消息的可靠性。解码包括：识别比特到检查消息的最小和第二最小模数，输出消息的符号和最不可靠的输入消息的位置，并且产生表示后验概率的消息的更新版本第i个检查对位消息中的最小或第二小的功能，所述输出消息的符号和所述最不可靠的传入消息的位置。

33. 发明授权

US07159170B2 LDPC (low density parity check) coded modulation symbol decoding 有权
标题翻译： LDPC（低密度奇偶校验）编码调制符号解码
公开(公告)号：US07159170B2
公开(公告)日：2007-01-02
申请号：US10668526
申请日：2003-09-23
申请人： Ba-Zhong Shen , Hau Thien Tran , Kelly Brian Cameron
发明人： Ba-Zhong Shen , Hau Thien Tran , Kelly Brian Cameron
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H04L27/2602 , G11B20/1833 , H03M13/1111 , H03M13/1117 , H03M13/112 , H03M13/25 , H03M13/255 , H03M13/256 , H03M13/258 , H03M13/2957 , H03M13/4161 , H03M13/45 , H03M13/6516 , H03M13/6583 , H04L1/0041 , H04L1/005 , H04L1/0058 , H04L1/006 , H04L1/1671 , H04L27/18
摘要： LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.
摘要翻译： LDPC（低密度奇偶校验）编码调制符号解码。通过适当地修改LDPC三部分图来消除比特节点从而生成LDPC二分图（使得符号节点被适当地映射到校验节点从而消除比特节点）来支持符号解码。将符号节点通信地耦合到校验节点的边缘被适当地标记以支持LDPC编码调制信号的符号解码。迭代解码处理可以包括更新校验节点以及估计符号序列和更新符号节点。在一些实施例中，可以执行替代的混合解码方法，使得执行位电平和符号电平解码的组合。该LDPC码解码仅执行比特解码。此外，它提供可比较或更好的比特解码性能，涉及相关度量的迭代更新。

34. 发明申请

US20040252791A1 LDPC (Low Density Parity Check) coded modulation hybrid decoding using non-Gray code maps for improved performance 有权
标题翻译：使用非格雷码的LDPC（低密度奇偶校验）编码调制混合解码，以提高性能
公开(公告)号：US20040252791A1
公开(公告)日：2004-12-16
申请号：US10802011
申请日：2004-03-16
发明人： Ba-Zhong Shen , Hau Thien Tran , Kelly Brian Cameron
IPC分类号： H04L005/12
CPC分类号： H04L1/005 , G11B20/1833 , H03M13/1102 , H03M13/1105 , H03M13/1117 , H03M13/112 , H03M13/25 , H03M13/255 , H03M13/256 , H03M13/258 , H03M13/2957 , H03M13/4161 , H03M13/45 , H03M13/6583 , H04L1/0041 , H04L1/0058 , H04L1/006 , H04L1/0071 , H04L1/1671 , H04L27/18 , H04L27/2602
摘要： LDPC (Low Density Parity Check) coded modulation hybrid decoding using non-Gray code maps for improved performance. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until sufficient degree of precision is achieved. The symbol node updating of the bit edge messages uses symbol metrics corresponding to the symbol being decoded and the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages uses the bit edge messages most recently updated by symbol node updating. The symbol node updating computes possible soft symbol estimates. LDPC coded modulation hybrid decoding can decode an LDPC-BICM (Low Density Parity Check-Bit Interleaved Coded Modulation) signal having a symbol mapped using non-Gray code mapping. By using the non-Gray code mapping, a performance improvement is achieved over an only Gray code mapping system.
摘要翻译：使用非格雷码的LDPC（低密度奇偶校验）编码调制混合解码，以提高性能。对于预定数量的解码迭代，或者直到达到足够的精度，连续替代地对位边消息执行检查节点更新和符号节点更新。比特边消息的符号节点更新使用与正被解码的符号相对应的符号度量和最近由校验节点更新更新的位边消息。位边消息的校验节点更新使用最近由符号节点更新更新的位边消息。符号节点更新计算可能的软符号估计。 LDPC编码调制混合解码可以解码具有使用非格雷码映射的符号映射的LDPC-BICM（低密度奇偶校验位交错编码调制）信号。通过使用非格雷码映射，仅通过格雷码映射系统实现性能提升。

35. 发明授权

US10868566B2 Error correction device, operating method of error correction device, and controller including error correction device 有权
公开(公告)号：US10868566B2
公开(公告)日：2020-12-15
申请号：US16100979
申请日：2018-08-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kyeongcheol Yang , Sunghye Cho , Youngjun Hwang , Junjin Kong , Hong Rak Son , Dong-Min Shin , Kijun Lee
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00 , H03M13/11 , H03M13/37
CPC分类号： H03M13/112 , H03M13/1117 , H03M13/1125 , H03M13/3715 , H03M13/3746 , H03M13/6577
摘要： An error correction device includes a low density parity check (LDPC) decoder and an adaptive decoding controller. The LDPC decoder iteratively performs LDPC decoding on data by using a decoding parameter. The adaptive decoding controller calculates an error rate depending on a result of the LDPC decoding and adjusts the decoding parameter depending on the error rate.

36. 发明授权

US10498363B2 Low density parity check decoder using binary logarithm and decoding method thereof 有权
公开(公告)号：US10498363B2
公开(公告)日：2019-12-03
申请号：US15803073
申请日：2017-11-03
申请人： Electronics and Telecommunications Research Institute
发明人： Hyuk Kim , Insan Jeon
IPC分类号： H03M13/11 , G06F17/13
CPC分类号： H03M13/1125 , H03M13/112 , H03M13/1108 , G06F17/13 , H03M13/114 , H03M13/1134
摘要： Provided is a low density parity check (LDPC) decoder. An LDPC decoder according to an embodiment of the inventive concept includes a variable node calculator for adding an input log-likelihood ratio (LLR) to message information of a check node to output the added values, a check node calculator for extracting signs of the output values of the variable node calculator, determining a minimum value of the output values, and calculating a correction term for the output values by using a binary logarithm to transmit to the variable node calculator, a hard decision block for determining bit values of the output values of the variable node calculator, and a parity check block for performing a parity check operation for determining validity of the bit value.

37. 发明申请

US20190190539A1 ERROR CORRECTION DEVICE, OPERATING METHOD OF ERROR CORRECTION DEVICE, AND CONTROLLER INCLUDING ERROR CORRECTION DEVICE 审中-公开
公开(公告)号：US20190190539A1
公开(公告)日：2019-06-20
申请号：US16100979
申请日：2018-08-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： KYEONGCHEOL YANG , SUNGHYE CHO , YOUNGJUN HWANG , JUNJIN KONG , HONG RAK SON , DONG-MIN SHIN , KIJUN LEE
IPC分类号： H03M13/11 , H03M13/37
CPC分类号： H03M13/112 , H03M13/1125 , H03M13/3746
摘要： An error correction device includes a low density parity check (LDPC) decoder and an adaptive decoding controller. The LDPC decoder iteratively performs LDPC decoding on data by using a decoding parameter. The adaptive decoding controller calculates an error rate depending on a result of the LDPC decoding and adjusts the decoding parameter depending on the error rate.

38. 发明申请

US20190097656A1 MIN-SUM DECODING FOR LDPC CODES 审中-公开
公开(公告)号：US20190097656A1
公开(公告)日：2019-03-28
申请号：US15903604
申请日：2018-02-23
申请人： SK hynix Inc.
发明人： Aman Bhatia , Naveen Kumar , Abhiram Prabhakar , Chenrong Xiong , Fan Zhang
IPC分类号： H03M13/11 , H03M13/00
CPC分类号： H03M13/1117 , H03M13/1108 , H03M13/112 , H03M13/1131 , H03M13/1177 , H03M13/616 , H03M13/6502
摘要： Techniques are described for performing a check node update (CNU) as part of iterative decoding of a low density-parity check (LDPC) code. The CNU uses a min-sum decoding approach that monitors whether two values received in messages from two variable nodes connected to a check nodes are equal and are the minimum value among the values received by the check nodes from other variable nodes connected thereto. Upon detecting such an event, the minimum value is adjusted by reducing it by an adjustment value to generate an adjusted minimum value. This adjusted minimum value approximates the minimum value that a sum-product algorithm (SPA) decoding approach would have generated. The adjusted minimum value is included in a response message sent from the check node to a variable node. The bit corresponding to that variable node is decoded based on this adjusted minimum value.

39. 发明授权

US09954559B2 Fixed point conversion of LLR values based on correlation 有权
公开(公告)号：US09954559B2
公开(公告)日：2018-04-24
申请号：US15404619
申请日：2017-01-12
申请人： Seagate Technology LLC
发明人： Yunxiang Wu , Yu Cai , Erich F. Haratsch
IPC分类号： G06F11/10 , H03M13/11 , H03M13/39 , G06F9/445 , H03M13/00
CPC分类号： H03M13/3927 , G06F8/65 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1044 , G06F11/1076 , H03M13/1111 , H03M13/1117 , H03M13/112 , H03M13/3905 , H03M13/6325 , H03M13/6577 , H03M13/658 , H03M13/6588 , H03M13/6591
摘要： An apparatus includes a memory and a controller. The memory may be configured to store data. The memory generally comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to generate a set of converted log likelihood ratios by scaling a set of original log likelihood ratios using a selected scalar value, wherein the controller determines the selected scalar value by generating a plurality of sets of scaled log likelihood ratios by scaling the set of original log likelihood ratios with a plurality of corresponding scalar values, calculating a plurality of respective correlation coefficients each measuring a similarity of a respective set of scaled log likelihood ratios to the set of original log likelihood ratios, and selecting the scalar value corresponding to the set of scaled log likelihood ratios whose respective correlation coefficient is highest as the selected scalar value.

40. 发明申请

US20180013446A1 METHOD AND SYSTEM FOR LDPC DECODING 审中-公开
公开(公告)号：US20180013446A1
公开(公告)日：2018-01-11
申请号：US15619764
申请日：2017-06-12
申请人： Maxlinear, Inc.
发明人： Mario Milicevic , Glenn Gulak
IPC分类号： H03M13/11 , H03M13/37
CPC分类号： H03M13/1174 , H03M13/112 , H03M13/1122 , H03M13/1128 , H03M13/114 , H03M13/116 , H03M13/3746 , H03M13/635 , H03M13/6502 , H03M13/6505 , H03M13/6516
摘要： A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.

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