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31. 发明授权

US5608402A Edge triggered sample and hold circuit and circuits constructed from same 失效
标题翻译：边沿触发采样保持电路和由其构成的电路
公开(公告)号：US5608402A
公开(公告)日：1997-03-04
申请号：US410227
申请日：1995-03-24
申请人： Robert J. Distinti
发明人： Robert J. Distinti
IPC分类号： H03M1/02 , H03M1/38 , H03M1/40 , H03M1/44 , H03M1/72
CPC分类号： H03M1/38 , H03M1/02 , H03M1/40 , H03M1/44 , H03M1/445 , H03M1/72
摘要： An Operational Analog to Digital (SYMAD) Convertor cell for converting an analog signal into a discrete binary code. An analog signal is processed by sample and hold circuitry and then compared to a reference voltage by a comparator. The comparator output is the converted digital output. This output is coupled back to the control input of an analog switch which selects either the reference voltage or a predetermined potential, typically zero volts, to couple to an inverting input of an operational amplifier. The analog signal input is also coupled to the non-inverting input of the operational amplifier. The operational amplifier is configured as a differential amplifier with a gain of two. If the digital output of the comparator is a logic 1, then the operational amplifier output is two times the difference between the analog signal and the reference voltage. If the digital output of the comparator is a logic 0, then the output of the operational amplifier is two times the analog signal. As many SYMAD cells as necessary may be provided to obtain a desired resolution.
摘要翻译：操作模数（SYMAD）转换单元，用于将模拟信号转换为离散二进制码。模拟信号由采样和保持电路处理，然后通过比较器与参考电压进行比较。比较器输出是转换的数字输出。该输出耦合回模拟开关的控制输入，模拟开关选择参考电压或预定电位（通常为零伏特）耦合到运算放大器的反相输入端。模拟信号输入也耦合到运算放大器的非反相输入端。运算放大器配置为增益为2的差分放大器。如果比较器的数字输出为逻辑1，则运算放大器输出是模拟信号与参考电压之差的两倍。如果比较器的数字输出为逻辑0，则运算放大器的输出为模拟信号的两倍。可以提供必要的许多SYMAD电池以获得期望的分辨率。

32. 发明授权

US5404143A Network swappers and circuits constructed from same 失效
标题翻译：网络交换器和电路由其构成
公开(公告)号：US5404143A
公开(公告)日：1995-04-04
申请号：US45815
申请日：1993-04-08
申请人： Robert J. Distinti
发明人： Robert J. Distinti
IPC分类号： G06N3/063 , G11C27/02 , H03M1/02 , H03M1/38 , H03M1/40 , H03M1/42 , H03M1/44 , H03M1/72 , H03M1/34
CPC分类号： H03M1/38 , G06N3/063 , G11C27/026 , H03M1/02 , H03M1/42 , H03M1/72 , H03M1/40 , H03M1/44 , H03M1/445
摘要： An n-bit analog processing circuit constructed with network swappers has n stages and an input port for inputting an analog signal to be processed. Each of the n stages includes first and second reference input ports, at least one swappable network having first and second terminals, and a switching element that is responsive to a digital input signal for varying a connectivity of the first and second terminals with respect to the first and second reference input ports. Each of the n networks has a primary electrical characteristic that is binarily weighted with respect to others of the networks. The primary electrical characteristic may be resistance, capacitance, capacitive reactance, inductance, inductive reactance, voltage potential, gain, transconductance, superconductance, time delay, permeability, electrical or optical conductor length, and/or winding turns. A characteristic of an analog signal appearing at an output port is a function of an analog signal applied between the first and second reference input ports of a most significant stage, and is also a function of an n-bit digital signal (binary or Gray code) that is applied to the n-stages.
摘要翻译：由网络交换器构成的n位模拟处理电路具有n个级和用于输入要处理的模拟信号的输入端口。 n个级中的每一个包括第一和第二参考输入端口，至少一个具有第一和第二端子的可交换网络，以及响应于数字输入信号的开关元件，用于改变第一和第二端子相对于第一和第二参考输入端口。 n个网络中的每一个具有相对于网络中的其他网络二次加权的主要电气特征。主要电气特性可以是电阻，电容，电抗，电感，感抗，电压电位，增益，跨导，超导，时间延迟，磁导率，电或光导体长度和/或绕组匝数。出现在输出端口的模拟信号的特征是施加在最重要级的第一和第二参考输入端口之间的模拟信号的函数，并且还是n位数字信号（二进制或格雷码）应用于n阶段。

33. 发明授权

US4524346A Circuit arrangement for converting an analog AC voltage signal to a digital signal 失效
标题翻译：用于将模拟AC电压信号转换为数字信号的电路装置
公开(公告)号：US4524346A
公开(公告)日：1985-06-18
申请号：US394980
申请日：1982-07-02
申请人： Hartmut Bosserhoff , Wolfgang Steinhagen , Ulrich Joeres
发明人： Hartmut Bosserhoff , Wolfgang Steinhagen , Ulrich Joeres
IPC分类号： H03M1/10 , H03M1/00 , H03K13/02
CPC分类号： H03M1/40 , H03M1/124 , H03M1/46
摘要： Analog AC to digital signal converter includes a sampling circuit which cyclically samples the analog AC signal to form analog sampling values, and an analog-digital converter for converting the analog sampling values to digital sampling values. A sign integrator integrates the sign of the digital sampling values, and a compensating voltage generator generates a compensating voltage in dependence upon the integration result. A combination circuit combines the compensating voltage with the analog sampling value from the sampling means and applies the combination result to the analog-digital converter. The circuit compensates any DC voltage component contained in the analog AC signal and avoids interferences resulting from such DC voltage component.
摘要翻译：模拟AC到数字信号转换器包括对模拟AC信号进行循环采样以形成模拟采样值的采样电路，以及用于将模拟采样值转换为数字采样值的模数转换器。符号积分器集成数字采样值的符号，补偿电压发生器根据积分结果产生补偿电压。组合电路将补偿电压与采样装置的模拟采样值相结合，并将组合结果应用于模数转换器。该电路补偿模拟AC信号中包含的任何直流电压分量，并避免由这种直流电压分量产生的干扰。

34. 发明授权

US4518949A Method of A/D conversion by successive approximations 失效
标题翻译：通过逐次逼近进行A / D转换的方法
公开(公告)号：US4518949A
公开(公告)日：1985-05-21
申请号：US504153
申请日：1983-06-14
申请人： Tetsuro Kanai
发明人： Tetsuro Kanai
IPC分类号： H03M1/38 , H03M1/00 , H03K13/03
CPC分类号： H03M1/40 , H03M1/46
摘要： An approximation control code is initially set to logic "1" except for the MSB which is set to logic "0". At the m-th comparison, if a sampled analog signal is greater than a comparison reference signal proportional to the control code, the m-th and (m+1)th MSBs of the control code are replaced by logics "1" and "0" respectively, and, if the sampled analog signal is less than the comparison reference signal, the (m+1)th MSB is replaced with logic "0".
摘要翻译：除了被设置为逻辑“0”的MSB之外，最初将近似控制码设置为逻辑“1”。在第m比较中，如果采样的模拟信号大于与控制码成比例的比较参考信号，则控制码的第m和第（m + 1）个MSB被逻辑“1”和“ 0“，并且如果采样的模拟信号小于比较参考信号，则将第（m + 1）个MSB替换为逻辑”0“。

35. 发明授权

US4498072A A/D Converter having a self-bias circuit 失效
标题翻译： A / D转换器具有自偏置电路
公开(公告)号：US4498072A
公开(公告)日：1985-02-05
申请号：US386786
申请日：1982-06-07
申请人： Masaru Moriyama
发明人： Masaru Moriyama
IPC分类号： H03M1/38 , H03M1/00 , H03M1/12 , H03K13/02
CPC分类号： H03M1/40 , H03M1/46
摘要： A self-bias circuit is employed for automatically changing the reference voltage of a comparator of an A/D converter of successive approximation type. The self-bias circuit is responsive to a voltage at a summing point where an input analog signal, an offset bias and an output analog signal from a D/A converter are added to each other. The self-bias circuit comprises a resistor and a capacitor so that the capacitor is charged by an average current passing through the resistor connected to the summing point, and the voltage across the capacitor will be used as the reference voltage of the comparator. When the input analog signal amplitude is small, the reference voltage is shifted so that noises superposed on the voltage at the summing point does not cause the comparator to produce an erroneous output signal with which the state of the MSB is undesirably changed. As the amplitude increases, the reference voltage rises for ensuring sufficient dynamic range and symmetrical operation for both positive and negative waves.
摘要翻译：自偏置电路用于自动改变逐次逼近型A / D变换器的比较器的参考电压。自偏置电路响应于加法点处的电压，其中来自D / A转换器的输入模拟信号，偏移偏置和输出模拟信号彼此相加。自偏置电路包括电阻器和电容器，使得电容器通过连接到求和点的电阻器的平均电流进行充电，电容器两端的电压将用作比较器的参考电压。当输入模拟信号振幅较小时，参考电压被移位，使得叠加在求和点上的电压的噪声不会导致比较器产生错误的输出信号，MSB的状态不利地改变。随着振幅的增加，参考电压升高以确保正，负波的动态范围和对称运行。

36. 发明授权

US4329679A Charge coupled device feedback analog-to-digital converter using successive approximations 失效
标题翻译：使用逐次逼近的电荷耦合器件反馈模数转换器
公开(公告)号：US4329679A
公开(公告)日：1982-05-11
申请号：US83421
申请日：1979-10-10
申请人： William E. Jensen
发明人： William E. Jensen
IPC分类号： H03M1/00 , H03K13/02
CPC分类号： H03M1/40 , H03M1/46
摘要： An analog-to-digital converter includes a charge coupled device comparator receiving an analog signal which is to be converted to an eight bit binary word. An eight bit charge coupled device shift register addresses an eight bit digital-to-analog converter through eight separate resettable latches to generate a reference signal which is compared in successive approximations to the analog signal by the charge coupled device comparator to generate each binary bit of the eight bit word. Sensitivity of the charge coupled device comparator is enhanced by the use of charge coupled regenerative feedback to generate each binary bit of the eight bit binary word, which is read serially into an output register. The charge coupled device comparator decides whether each bit of the eight bit binary word is to be a logic one or a logic zero by comparing the analog input signal with reference signals selected in successive approximations by a shift register addressing the digital-to-analog converter. The analog signal is compared with a progressively increasing reference signal whose magnitude is increased by successively smaller increments. Eight such successive approximations and comparisons are made in order to generate the eight bit binary word.
摘要翻译：模数转换器包括电容耦合器件比较器，其接收要转换为八位二进制字的模拟信号。八位电荷耦合器件移位寄存器通过八个单独的可复位锁存器寻址八位数模转换器，以产生参考信号，该参考信号通过电荷耦合器件比较器在逐次逼近模拟信号中进行比较，以产生每个二进制位八位字。电荷耦合器件比较器的灵敏度通过使用电荷耦合的再生反馈来产生串行读入输出寄存器的八位二进制字的每个二进制位来增强。电荷耦合器件比较器通过将模拟输入信号与通过寻址数模转换器的移位寄存器在逐次逼近中选择的参考信号相比较来判定八位二进制字的每个位是逻辑1还是逻辑零。将模拟信号与逐渐增加的参考信号进行比较，其参数信号的幅度依次递增。进行八次这样的逐次逼近和比较以便产生八位二进制字。

37. 发明授权

US4308524A Fast high resolution predictive analog-to-digital converter with error correction 失效
标题翻译：具有纠错功能的快速高分辨率预测模数转换器
公开(公告)号：US4308524A
公开(公告)日：1981-12-29
申请号：US45793
申请日：1979-06-05
申请人： William D. Harrison , Henry H. Martin
发明人： William D. Harrison , Henry H. Martin
IPC分类号： H03M1/10 , H03M1/00 , H03K13/02
CPC分类号： H03M1/40 , H03M1/46
摘要： An analog-to-digital conversion system uses a fast analog-to-digital converter having a resolution less than the system resolution to convert the difference between a previously predicted value and the current analog value. The converted difference is summed with the predicted value to compute the actual value of the analog input signal to a resolution greater than that of the fast analog-to-digital converter. The high resolution digital value thus obtained becomes the predicted value for the next conversion. This predicted value is converted by a digital-to-analog converter having the same accuracy but not the same resolution as the system output to an analog signal which is compared with the input analog signal to obtain a difference signal. This difference signal is sampled and held to provide the input to the fast analog-to-digital converter. The system includes a gain scaling and switching circuit to compensate for errors which would occur when the difference between the true analog input and the prediction exceeds the range of the low resolution, fast analog-to-digital converter.
摘要翻译：模数转换系统使用具有小于系统分辨率的分辨率的快速模数转换器来转换先前预测值和当前模拟值之间的差值。转换的差值与预测值相加，以将模拟输入信号的实际值计算为高于快速模数转换器的分辨率。这样获得的高分辨率数字值成为下一转换的预测值。该预测值由具有与输入模拟信号相比较的系统输出相同的精度但不同分辨率的数模转换器转换，以获得差分信号。该差分信号被采样和保持以向快速模数转换器提供输入。该系统包括增益缩放和切换电路，以补偿当真实模拟输入和预测之间的差超过低分辨率，快速模数转换器的范围时将发生的错误。

38. 发明授权

US4293848A MOS Analog-to-digital converter 失效
标题翻译： MOS模数转换器
公开(公告)号：US4293848A
公开(公告)日：1981-10-06
申请号：US80284
申请日：1979-10-01
申请人： Edmund K. Cheng , Wiley E. Hill
发明人： Edmund K. Cheng , Wiley E. Hill
IPC分类号： H03M1/00 , H03K13/02
CPC分类号： H03M1/40 , H03M1/46 , H03M1/785
摘要： An MOS, integrated circuit, analog-to-digital converter powered by a single power supply potential and suitable for converting an analog signal equal to that power supply potential is described. The input analog signal is capacitively divided by two; resistor strings interlaced with the resistance ladder of the digital-to-analog converter provides a reduced reference potential. A chopper amplifier is employed in the comparator which includes circuits for reducing offset potentials.
摘要翻译：描述了由单个电源电位供电且适于转换等于该电源电位的模拟信号的MOS集成电路模数转换器。输入模拟信号电容性除以2; 与数/模转换器的电阻梯形图交错的电阻串提供了降低的参考电位。在比较器中采用斩波放大器，其包括用于减小偏移电位的电路。

39. 发明授权

US4209774A Apparatus for converting a DC or analog signal to a digital signal with minimum drift 失效
标题翻译：用于将DC或模拟信号转换为具有最小漂移的数字信号的装置
公开(公告)号：US4209774A
公开(公告)日：1980-06-24
申请号：US884210
申请日：1978-03-07
申请人： Robert K. Bendler
发明人： Robert K. Bendler
IPC分类号： H03M1/00 , H03K13/02
CPC分类号： H03M1/0607 , H03M1/40
摘要： Apparatus for converting a dc or analog signal from, for example, a resistance type temperature detector, includes an analog to digital converter which has zero temperature drift. This is achieved by the use of two identical successive approximation digital to analog converters with an external comparator connected to both converters at the same time. By switching, one converter is used to provide zero compensation the other converter being inactive except for utilizing it as the path for the amplifier drift current; then with the switch in its other phase the other converter is activated to convert the analog signal to digital format taking into account the previously computed drift signal.
摘要翻译：用于转换来自例如电阻型温度检测器的直流或模拟信号的装置包括具有零温度漂移的模数转换器。这通过使用两个相同的逐次逼近数模转换器来实现，其中外部比较器同时连接到两个转换器。通过切换，除了将其用作放大器漂移电流的路径之外，一个转换器用于提供零补偿，另一个转换器是无效的。然后在开关处于另一相位的情况下，另一个转换器被激活，以将模拟信号转换为数字格式，同时考虑到先前计算的漂移信号。

40. 发明授权

US3971015A Recirculating type analog to digital converter 失效
标题翻译：循环型模数转换器
公开(公告)号：US3971015A
公开(公告)日：1976-07-20
申请号：US548315
申请日：1975-02-10
申请人： Thomas Hornak
发明人： Thomas Hornak
IPC分类号： H03M1/40 , H03M1/00 , H03K13/02
CPC分类号： H03M1/40
摘要： An analog to digital converter includes a comparator coupled to a cascade having in serial connection an analog switch, a time delay and an algorithmic coder. The algorithmic coder generates a signal at a first output which is an inverse of a signal appearing at the time delay input and a second output which is a selected function of a signal appearing at the time delay input corresponding to a desired conversion. An analog signal to be converted is applied to the time delay input and the first and second algorithmic coder outputs are sequentially passed through the cascade.
摘要翻译：模数转换器包括耦合到具有串行连接的模拟开关，时间延迟和算法编码器的级联的比较器。算法编码器在第一输出处产生信号，该信号是在时间延迟输入处出现的信号的倒数，而第二输出是对应于期望转换的时间延迟输入处出现的信号的选定函数。要转换的模拟信号被施加到时间延迟输入，并且第一和第二算法编码器输出顺序地通过级联。

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