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31. 发明授权

US08054115B2 Phase-locked loop integrated circuits having dual feedback control 有权
标题翻译：具有双重反馈控制的锁相环集成电路
公开(公告)号：US08054115B2
公开(公告)日：2011-11-08
申请号：US12571868
申请日：2009-10-01
申请人： Jong-shin Shin
发明人： Jong-shin Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0895 , H03L7/087 , H03L7/18
摘要： Phase-locked loop (PLL) integrated circuits according to embodiments of the invention provide dual feedback control. The first feedback control utilizes a conventional phase locking scheme that passes a feedback clock signal to an input of a phase-frequency detector (PFD). The second feedback control utilizes an automatic frequency calibrator that evaluates a frequency of an output of a voltage-controlled oscillator (VCO) relative to a locked frequency detected during calibration and provides separate calibration control to a charge pump.
摘要翻译：根据本发明的实施例的锁相环（PLL）集成电路提供双重反馈控制。第一反馈控制利用将反馈时钟信号传递到相位频率检测器（PFD）的输入的常规锁相方案。第二反馈控制使用自动频率校准器，其相对于在校准期间检测到的锁定频率来评估压控振荡器（VCO）的输出的频率，并向电荷泵提供单独的校准控制。

32. 发明授权

US08040167B1 Method and apparatus for charge leakage compensation for charge pump 有权
标题翻译：电荷泵充电泄漏补偿方法和装置
公开(公告)号：US08040167B1
公开(公告)日：2011-10-18
申请号：US12732211
申请日：2010-03-26
申请人： Chia-Liang Lin , Gerchih Chou
发明人： Chia-Liang Lin , Gerchih Chou
IPC分类号： H03L7/00
CPC分类号： H03L7/0895
摘要： An apparatus is disclosed, the apparatus comprising: a charge pump for receiving a phase signal representing a result of a phase detection and for outputting a current flowing between an internal node and an output node; a capacitive load shunt at the output node; a current source controlled by a bias voltage for outputting a compensation current to the internal node; a current sensor inserted between the internal node and the output node for sensing the current; and a feedback network for adjusting the bias voltage in accordance with an output of the current sensor.
摘要翻译：公开了一种装置，该装置包括：电荷泵，用于接收表示相位检测结果的相位信号，并输出在内部节点和输出节点之间流动的电流; 输出节点处的电容负载分流; 由偏置电压控制的电流源，用于向内部节点输出补偿电流; 插入在内部节点和输出节点之间的电流传感器用于感测电流; 以及用于根据电流传感器的输出来调整偏置电压的反馈网络。

33. 发明授权

US07944257B2 Method and system of optimizing a control system using low voltage and high-speed switching 有权
标题翻译：使用低电压和高速切换优化控制系统的方法和系统
公开(公告)号：US07944257B2
公开(公告)日：2011-05-17
申请号：US12465808
申请日：2009-05-14
申请人： I-chang (Bart) Wu
发明人： I-chang (Bart) Wu
IPC分类号： H03L7/06
CPC分类号： H03L7/0895
摘要： A phase-locked loop charge pump driven by low voltage input is disclosed. In one aspect, a charge pump for a phase-locked loop circuit includes a sourcing current source providing a sourcing current, wherein the sourcing current source is coupled to a high-voltage operating voltage supply. A sourcing control circuit uses low-voltage sourcing control signals to selectively cause the charge pump to source the sourcing current to an output of the charge pump. A sinking control circuit uses low-voltage sinking control signals at a low voltage and utilizes a low-swing current mechanism to sink the sinking current from the output of the charge pump. In another aspect, the sourcing control circuit is cascode and the sinking circuit is non-cascode. In another aspect the sourcing current source and the sinking current source are both cascode. In another aspect, the sourcing current source is non-cascode and the sinking current source is cascode. In another aspect, the sourcing current source and the sinking current source are both non-cascode.
摘要翻译：公开了一种由低电压输入驱动的锁相环电荷泵。一方面，用于锁相环电路的电荷泵包括提供源极电流的源极电流源，其中源极电流源耦合到高压工作电压源。采购控制电路使用低电压源控制信号来选择性地使电荷泵将电源电流输送到电荷泵的输出端。下沉控制电路使用低电压的低压吸收控制信号，并利用低摆动电流机制来从电荷泵的输出吸收吸收电流。在另一方面，源控制电路是共源共栅，而吸收电路是非共源共栅。在另一方面，源电流源和吸收电流源都是共源共栅。另一方面，源电流源为非共源共栅，并且吸收电流源为共源共栅。另一方面，源电流源和吸收电流源都是非共源共栅。

34. 发明申请

US20110102034A1 CHARGE PUMP FOR PLL/DLL 有权
标题翻译： PLL / DLL充电泵
公开(公告)号：US20110102034A1
公开(公告)日：2011-05-05
申请号：US12986646
申请日：2011-01-07
申请人： Dieter Haerle
发明人： Dieter Haerle
IPC分类号： H03L7/06
CPC分类号： H03L7/0895 , H03L7/0812
摘要： A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.
摘要翻译：用于锁相环/延迟锁定环的电荷泵通过使用运算放大器将静态相位误差最小化。运算放大器还可以减轻低电源电压的影响。

35. 发明授权

US07893737B2 Charge pump for PLL/DLL 有权
公开(公告)号：US07893737B2
公开(公告)日：2011-02-22
申请号：US12714670
申请日：2010-03-01
申请人： Dieter Haerle
发明人： Dieter Haerle
IPC分类号： H03L7/06
CPC分类号： H03L7/0895 , H03L7/0812
摘要： A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

36. 发明申请

US20110032009A1 DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：延迟锁定环路
公开(公告)号：US20110032009A1
公开(公告)日：2011-02-10
申请号：US12844620
申请日：2010-07-27
申请人： Masaaki Iwane
发明人： Masaaki Iwane
IPC分类号： H03L7/085
CPC分类号： H03L7/0816 , H03L7/0891 , H03L7/0895 , H03L7/095 , H03L2207/14
摘要： A delay locked loop circuit comprising a VCDL which outputs a feedback clock by delaying an input clock in accordance with a magnitude of a control voltage, a phase comparator which detects a phase difference between the feedback clock and a reference clock by comparing the feedback clock with the reference clock, and outputs an Up-signal for raising the control voltage and a Down-signal for lowering the control voltage in accordance with the phase difference, a control voltage generation circuit which determines the control voltage in accordance with the Up-signal and the Down-signal, and outputs the control voltage to the VCDL, and a reset circuit which resets the phase comparator based on a logical OR between the reference clock and a first intermediate clock which is a signal obtained by delaying the input clock by the VCDL and is output before the feedback clock.
摘要翻译：一种延迟锁定环电路，包括通过根据控制电压的幅度延迟输入时钟来输出反馈时钟的VCDL;相位比较器，其通过将反馈时钟与参考时钟进行比较来检测反馈时钟与参考时钟之间的相位差参考时钟，并输出用于提高控制电压的Up信号和用于根据相位差降低控制电压的Down信号;控制电压发生电路，其根据Up信号确定控制电压;以及 Down信号，并将控制电压输出到VCDL;以及复位电路，其基于参考时钟与作为通过VCDL延迟输入时钟而获得的信号的第一中间时钟之间的逻辑或复位相位比较器并在反馈时钟之前输出。

37. 发明授权

US07884658B2 Circuits for forming the inputs of a latch 有权
标题翻译：用于形成闩锁输入的电路
公开(公告)号：US07884658B2
公开(公告)日：2011-02-08
申请号：US12060190
申请日：2008-03-31
申请人： Peter Kinget , Shih-an Yu
发明人： Peter Kinget , Shih-an Yu
IPC分类号： H03K3/356
CPC分类号： H03K3/356043 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1265 , H03B5/1293 , H03J2200/10 , H03K23/667 , H03L7/0891 , H03L7/0895 , H03L7/1976 , H03M7/3022
摘要： Circuits for forming the inputs of a latch are provided. In some embodiments, circuits for forming inputs of a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common mode level at the first gate terminal, wherein the first gate terminal provides a data input to the latch; and a second transistor having a second gate terminal, a second drain terminal, a second source terminal, a second gate length, and a second common mode level at the second gate terminal, wherein the second gate terminal provides a clock input to the latch, the second drain terminal is coupled to the first source terminal, and the first gate length and the second gate length are sized so that the first common model level and the second common mode level are substantially equal.
摘要翻译：提供了用于形成锁存器的输入的电路。在一些实施例中，用于形成锁存器的输入的电路包括：在第一栅极端子处具有第一栅极端子，第一漏极端子，第一源极端子，第一栅极长度和第一共模电平的第一晶体管，其中第一门极端子向锁存器提供数据输入; 以及在所述第二栅极端子处具有第二栅极端子，第二漏极端子，第二源极端子，第二栅极长度和第二共模电平的第二晶体管，其中所述第二栅极端子为所述锁存器提供时钟输入，所述第二漏极端子耦合到所述第一源极端子，并且所述第一栅极长度和所述第二栅极长度的尺寸设定成使得所述第一共模型电平和所述第二共模电平基本相等。

38. 发明申请

US20100289593A1 CLOCK AND DATA RECOVERY CIRCUIT 有权
标题翻译：时钟和数据恢复电路
公开(公告)号：US20100289593A1
公开(公告)日：2010-11-18
申请号：US12536448
申请日：2009-08-05
申请人： I-Fong Chen , Shen-Iuan Liu
发明人： I-Fong Chen , Shen-Iuan Liu
IPC分类号： H03L7/099
CPC分类号： H03L7/0895 , H03L7/0802
摘要： An embodiment of the invention provides a clock and data recovery circuit. The clock and data recovery circuit comprises a phase detector, a pre-accumulator, a register, an accumulator and a digital controlled oscillator. By using the transmission path formed by the pre-accumulator, the output of the phase detector can be transmitted to the digital controlled oscillator in advance to adjust the frequency of its output clock signal and the latency due to the accumulator can be reduced.
摘要翻译：本发明的实施例提供了一种时钟和数据恢复电路。时钟和数据恢复电路包括相位检测器，预累加器，寄存器，累加器和数字控制振荡器。通过使用由预累加器形成的传输路径，可以提前将相位检测器的输出发送到数字控制振荡器，以调整其输出时钟信号的频率，并且可以减少由于累加器引起的等待时间。

39. 发明申请

US20100289539A1 METHOD AND SYSTEM OF OPTIMIZING A CONTROL SYSTEM USING LOW VOLTAGE AND HIGH-SPEED SWITCHING 有权
标题翻译：使用低电压和高速开关优化控制系统的方法和系统
公开(公告)号：US20100289539A1
公开(公告)日：2010-11-18
申请号：US12465808
申请日：2009-05-14
申请人： I-chang Bart WU
发明人： I-chang Bart WU
IPC分类号： H03L7/06
CPC分类号： H03L7/0895
摘要： A phase-locked loop charge pump driven by low voltage input is disclosed. In one aspect, a charge pump for a phase-locked loop circuit includes a sourcing current source providing a sourcing current, wherein the sourcing current source is coupled to a high-voltage operating voltage supply. A sourcing control circuit uses low-voltage sourcing control signals to selectively cause the charge pump to source the sourcing current to an output of the charge pump. A sinking control circuit uses low-voltage sinking control signals at a low voltage and utilizes a low-swing current mechanism to sink the sinking current from the output of the charge pump. In another aspect, the sourcing control circuit is cascode and the sinking circuit is non-cascode. In another aspect the sourcing current source and the sinking current source are both cascode. In another aspect, the sourcing current source is non-cascode and the sinking current source is cascode. In another aspect, the sourcing current source and the sinking current source are both non-cascode.
摘要翻译：公开了一种由低电压输入驱动的锁相环电荷泵。一方面，用于锁相环电路的电荷泵包括提供源极电流的源极电流源，其中源极电流源耦合到高压工作电压源。采购控制电路使用低电压源控制信号来选择性地使电荷泵将电源电流输送到电荷泵的输出端。下沉控制电路使用低电压的低压吸收控制信号，并利用低摆动电流机制来从电荷泵的输出吸收吸收电流。在另一方面，源控制电路是共源共栅，而吸收电路是非共源共栅。在另一方面，源电流源和吸收电流源都是共源共栅。另一方面，源电流源为非共源共栅，并且吸收电流源为共源共栅。另一方面，源电流源和吸收电流源都是非共源共栅。

40. 发明申请

US20100264964A1 Pll circuit 有权
标题翻译： Pll电路
公开(公告)号：US20100264964A1
公开(公告)日：2010-10-21
申请号：US12662042
申请日：2010-03-29
申请人： Atsushi Furuta
发明人： Atsushi Furuta
IPC分类号： H03L7/07
CPC分类号： H03L7/0895 , H03L7/0893 , H03L7/099 , H03L7/107 , H03L7/1075
摘要： There is provided a PLL circuit including a first loop filter and a second loop filter, which includes a current signal generation circuit that includes a first output driver that generates a first current signal to be output to the first loop filter and a second output driver that generates a second current signal to be output to the second loop filter, and a control circuit that selects which of the first output driver and the second output driver is to be activated.
摘要翻译：提供了包括第一环路滤波器和第二环路滤波器的PLL电路，其包括电流信号产生电路，该电流信号产生电路包括产生要输出到第一环路滤波器的第一电流信号的第一输出驱动器和第二输出驱动器，产生要输出到第二环路滤波器的第二电流信号，以及选择要激活第一输出驱动器和第二输出驱动器中的哪一个的控制电路。

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