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31. 发明申请

US20150358008A1 Linearity of Phase Interpolators using Capacitive Elements 有权
标题翻译：使用电容元素的相位插值器的线性度
公开(公告)号：US20150358008A1
公开(公告)日：2015-12-10
申请号：US14300119
申请日：2014-06-09
申请人： Qualcomm Incorporated
发明人： Li Sun , Zhi Zhu , Xiaohua Kong
IPC分类号： H03K5/13 , H04L7/02
CPC分类号： H03K5/13 , H03K2005/00052 , H03K2005/00286 , H04L7/0025 , H04L7/02
摘要： A phase interpolator, including: a pair of load resistors coupled to a supply voltage; a plurality of branches coupled to the pair of load resistors, each branch including a differential pair of transistors connected at source terminal to form a source node; a plurality of tail current sources, each tail current source coupled to one of the source nodes; and a plurality of coupling capacitors, each coupling capacitor coupled between the source nodes in two adjacent branches of the plurality of branches.
摘要翻译：一种相位插值器，包括：耦合到电源电压的一对负载电阻; 耦合到所述一对负载电阻器的多个分支，每个分支包括在源极端子处连接以形成源节点的差分对晶体管; 多个尾流源，每个尾电流源耦合到源节点之一; 以及多个耦合电容器，每个耦合电容器耦合在所述多个分支的两个相邻分支中的源节点之间。

32. 发明申请

US20150280699A1 LINEARIZATION CIRCUIT FOR HIGH FREQUENCY SIGNAL PHASE ADJUSTMENT 有权
标题翻译：用于高频信号相位调整的线性化电路
公开(公告)号：US20150280699A1
公开(公告)日：2015-10-01
申请号：US14228495
申请日：2014-03-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： SATOSHI SAKURAI
IPC分类号： H03K5/13 , H03K17/687
CPC分类号： H03K5/13 , H03K17/687
摘要： A circuit includes a phase adjustment capacitor (PAC) coupled to a signal path and configured to adjust a phase of a signal on the signal path. A transistor switch device is coupled in series with the PAC to provide a circuit branch parallel with the signal path. The transistor switch device is configured to selectively open or close the circuit branch of the signal path to enable or disable, respectively, the adjustment of the phase of the signal on the signal path via the PAC. A nonlinear capacitance is coupled to a node interconnecting the PAC and the transistor switch device. The nonlinear capacitance is configured to vary inversely proportional with a capacitance of the transistor switch device with respect to the signal on the signal path and to linearize a total capacitance provided by the circuit branch when the circuit branch is open.
摘要翻译：电路包括耦合到信号路径并被配置为调整信号路径上的信号的相位的相位调整电容器（PAC）。晶体管开关器件与PAC串联耦合以提供与信号通路并联的电路支路。晶体管开关器件被配置为选择性地打开或关闭信号路径的电路分支，以分别启用或禁用经由PAC对信号路径上的信号的相位的调整。非线性电容耦合到互连PAC和晶体管开关器件的节点。非线性电容被配置为与晶体管开关器件相对于信号路径上的信号的电容成反比，并且当电路分支断开时线性化由电路支路提供的总电容。

33. 发明申请

US20150229327A1 MULTIPLEXER 审中-公开
标题翻译：复用器
公开(公告)号：US20150229327A1
公开(公告)日：2015-08-13
申请号：US14179341
申请日：2014-02-12
申请人： FUJITSU LIMITED
发明人： Nikola NEDOVIC
IPC分类号： H03M9/00 , H03K5/13
CPC分类号： H03M9/00 , H03K5/13
摘要： A multiplexer may include a first circuit, a second circuit, and a third circuit. The first circuit may be configured to receive a first input signal and a first trigger signal and to output a first output signal that may be based on the first input signal during a first level of the first trigger signal and may be at a known level during a second level of the first trigger signal. The second circuit may be configured to receive a second input signal and a second trigger signal and to output a second output signal that may be based on the second input signal during a first level of the second trigger signal and may be at the known level during a second level of the second trigger signal. The third circuit may be configured to output a third output signal based on the first and second output signals.
摘要翻译：多路复用器可以包括第一电路，第二电路和第三电路。第一电路可以被配置为接收第一输入信号和第一触发信号，并且在第一触发信号的第一电平期间输出可以基于第一输入信号的第一输出信号，并且可以在第一触发信号期间处于已知电平第一级触发信号。第二电路可以被配置为接收第二输入信号和第二触发信号，并且在第二触发信号的第一电平期间输出可以基于第二输入信号的第二输出信号，并且可以在第二触发信号期间处于已知电平第二级触发信号。第三电路可以被配置为基于第一和第二输出信号输出第三输出信号。

34. 发明授权

US09024672B2 Signal processing apparatus and signal processing method 有权
标题翻译：信号处理装置及信号处理方法
公开(公告)号：US09024672B2
公开(公告)日：2015-05-05
申请号：US14482522
申请日：2014-09-10
申请人： Canon Kabushiki Kaisha
发明人： Koji Kawamura
IPC分类号： G06F1/04 , H03K5/13 , H03K5/1252 , G01D5/347
CPC分类号： H03K5/13 , G01D5/3473 , H03K5/1252
摘要： Digital signals with higher resolution are generated from dual-phase encode signals indicating phase changes of a position or an angle of a target. A signal processing apparatus for processing dual-phase encode signals indicating changes in position of a target, comprises: a first noise reduction unit configured to remove high frequency noise from each of the dual-phase encode signals before interpolation processing; an interpolating unit configured to apply interpolation processing to the dual-phase encode signals output from the first noise reduction unit to generate dual-phase encode signals with higher resolution; and a second noise reduction unit configured to remove noise from the dual-phase encode signals output from the interpolating unit.
摘要翻译：具有较高分辨率的数字信号是从指示目标的位置或角度的相位变化的双相位编码信号产生的。一种用于处理指示目标位置变化的双相编码信号的信号处理装置，包括：第一噪声降低单元，被配置为在插值处理之前从每个双相编码信号中去除高频噪声; 内插单元，被配置为对从第一噪声降低单元输出的双相位编码信号应用内插处理，以产生具有更高分辨率的双相编码信号; 以及第二降噪单元，被配置为从所述内插单元输出的双相编码信号中去除噪声。

35. 发明授权

US08941420B2 Low-latency, frequency-agile clock multiplier 有权
标题翻译：低延迟，频率敏捷的时钟倍频器
公开(公告)号：US08941420B2
公开(公告)日：2015-01-27
申请号：US13983836
申请日：2012-05-24
申请人： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
发明人： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
IPC分类号： H03B19/00 , H03K5/00 , H03L7/06 , H03L7/099
CPC分类号： H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
摘要： In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
摘要翻译：在第一时钟频率倍增器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现基本上比孤立的国际劳工组织的输入频率范围更宽的集体输入频率范围。在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择时钟。

36. 发明授权

US08798222B2 Methods and apparatus for digital linearization of an analog phase interpolator 有权
标题翻译：用于数字线性化模拟相位内插器的方法和装置
公开(公告)号：US08798222B2
公开(公告)日：2014-08-05
申请号：US11095770
申请日：2005-03-31
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Craig B. Ziemer
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Craig B. Ziemer
IPC分类号： H04L7/00
CPC分类号： H03K5/13 , H03K2005/00052 , H04L7/00
摘要： Methods and apparatus are provided for digital linearization of an analog phase interpolator. Up to 2N desired phase values are mapped to a corresponding M bit value, where M is greater than N. A corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2N desired phase values. A linearized phase interpolator is also provided that accounts for process, voltage, temperature or aging (PVTA) variations.
摘要翻译：提供了用于模拟相位内插器的数字线性化的方法和装置。多达2N个所需的相位值被映射到对应的M位值，其中M大于N.相应的M位值被施加到相位内插器以获得期望的2N个期望相位值。还提供了线性化相位内插器，其考虑过程，电压，温度或老化（PVTA）变化。

37. 发明授权

US08638124B1 Clock phase shift detector 失效
标题翻译：时钟相移检测器
公开(公告)号：US08638124B1
公开(公告)日：2014-01-28
申请号：US13707748
申请日：2012-12-07
申请人： International Business Machines Corporation
发明人： Kai D. Feng , Jon-ru Guo , Trushil N. Shah , Ping-Chuan Wang , Zhijian Yang
IPC分类号： G01R25/00 , H03K5/13
CPC分类号： G01R25/00 , G01R31/31727 , G01R31/318552 , H03K5/13 , H03L7/081 , H03L7/085
摘要： A clock phase shift detector circuit may include a phase detector for generating a phase signal based on a phase difference between first and second clock signals. A current mirror having a first, a second, and a third integrator may be coupled to the phase detector, whereby the first integrator integrates the first clock signal and generates a first voltage, the second integrator integrates the first clock signal and generates a second voltage, and the third integrator integrates the phase signal and generates a third voltage. A first comparator receives the first and the third voltage, and generates a first control signal. A second comparator receives the second and the third voltage, and generates a second control signal. The first and second control signals may detect a change between the phase difference of the first and the second clock signal and an optimized phase difference.
摘要翻译：时钟相移检测器电路可以包括相位检测器，用于基于第一和第二时钟信号之间的相位差产生相位信号。具有第一，第二和第三积分器的电流镜可以耦合到相位检测器，由此第一积分器对第一时钟信号进行积分并产生第一电压，第二积分器对第一时钟信号进行积分并产生第二电压并且第三积分器对相位信号进行积分并产生第三电压。第一比较器接收第一和第三电压，并产生第一控制信号。第二比较器接收第二和第三电压，并产生第二控制信号。第一和第二控制信号可以检测第一和第二时钟信号的相位差和优化的相位差之间的变化。

38. 发明授权

US08614465B2 Electronic device and manufacturing method 有权
标题翻译：电子器件及制造方法
公开(公告)号：US08614465B2
公开(公告)日：2013-12-24
申请号：US13027977
申请日：2011-02-15
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： H01L29/66
CPC分类号： H01L29/788 , H01L21/28273 , H01L22/14 , H01L22/20 , H03K5/13
摘要： Provided is an electronic device that generates an output signal corresponding to an input signal, comprising a signal processing section that receives the input signal and outputs the output signal corresponding to the input signal, and a floating electrode that accumulates a charge by being irradiated by an electron beam. The signal processing section adjusts electric characteristics of the output signal according to a charge amount accumulated in the floating electrode, and includes a transistor formed on the semiconductor substrate between an input terminal that receives the input signal and an output terminal that outputs the output signal. The floating electrode is formed between a gate electrode of the transistor and the semiconductor substrate.
摘要翻译：提供一种电子设备，其产生与输入信号相对应的输出信号，包括：信号处理部，其接收输入信号并输出与输入信号对应的输出信号;以及浮动电极，其通过被电子束。信号处理部根据在浮置电极中累积的电荷量调节输出信号的电特性，并且包括在接收输入信号的输入端子与输出输出信号的输出端子之间形成在半导体基板上的晶体管。浮置电极形成在晶体管的栅电极和半导体衬底之间。

39. 发明授权

US08587344B2 Power efficient multiplexer 有权
公开(公告)号：US08587344B2
公开(公告)日：2013-11-19
申请号：US13356396
申请日：2012-01-23
申请人： Robert Paul Masleid
发明人： Robert Paul Masleid
IPC分类号： H03K19/094 , H03K19/20
CPC分类号： H03K5/133 , H03K5/13 , H03K17/005 , H03K17/6872 , H03K2005/00156 , H03K2217/0036
摘要： A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

40. 发明申请

US20130300483A1 METHODS AND DEVICES RELATING TO TIME-VARIABLE SIGNAL PROCESSING 有权
标题翻译：与时变信号处理相关的方法和设备
公开(公告)号：US20130300483A1
公开(公告)日：2013-11-14
申请号：US13890649
申请日：2013-05-09
申请人： The Royal Institution for the Advancement of Learning / McGill University
发明人： Gordon Roberts , Mohammad Ali Bakhshian
IPC分类号： H03K3/86
CPC分类号： H03K3/86 , H03K5/13 , H03K2005/00032 , H03K2005/00052
摘要： Time-Mode Signal Processing (TMSP) offers a means for offsetting some of the challenges for analog circuit designs when exploiting CMOS circuit processes designed for digital applications. It would therefore be beneficial to provide a digital method for the storage, addition and subtraction of Time-Mode variables as these offer significant benefit to providing TMSP techniques and expanding their exploitation within devices, systems, and applications. Whilst driven by CMOS process challenges the TM circuits outlined may exploit essentially any digital circuit technology since they are based upon delay. The inventors present an approach to TM variables wherein a switched delay unit is exploited and adopted such that the instantaneous phase difference between two rising signal edges can be latched and used to perform various arithmetic operations. Beneficially, the technique allows analog sampled-data signal processing to be implemented within digital circuitry.
摘要翻译：时间模式信号处理（TMSP）提供了一种在利用为数字应用设计的CMOS电路工艺时，抵消模拟电路设计中的一些挑战的手段。因此，提供用于存储，加减时间模式变量的数字方法将是有益的，因为它们提供了提供TMSP技术并扩展其在设备，系统和应用中的利用的显着优点。在CMOS工艺挑战的驱动下，概述的TM电路基本上可以利用任何数字电路技术，因为它们基于延迟。本发明人提出了一种TM变量的方法，其中开关和采用开关延迟单元，使得两个上升信号边沿之间的瞬时相位差可被锁存并用于执行各种算术运算。有利的是，该技术允许在数字电路内实现模拟采样数据信号处理。

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