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31. 发明授权

US06208166B1 Circuit and method for implementing combinatorial logic functions 失效
标题翻译：实现组合逻辑功能的电路和方法
公开(公告)号：US06208166B1
公开(公告)日：2001-03-27
申请号：US09268086
申请日：1999-03-12
申请人： Fernando Incertis Carro
发明人： Fernando Incertis Carro
IPC分类号： H03K1900
CPC分类号： H03K19/1736
摘要： A Transfer Logic Cell (TLC) circuit performing non-boolean logic elementary operations between a dual-rail input and a dual-rail output upon assertion of signals on at least one control terminal to operate said circuit into one of four logic modes of operation i.e. a ‘PASS’, ‘LEFT’, ‘CROSS’ or ‘RIGHT’ mode or in one of two non-logic modes i.e. ‘ISOLATION’ or ‘TRANSPARENT’ mode or in any subset of combinations of the herein above modes. And a method for assembling a plurality of TLC circuits to carry out logic functions in an array-like structure.
摘要翻译：传输逻辑单元（TLC）电路在至少一个控制终端上断言信号时执行双轨输入和双轨输出之间的非布尔逻辑基本操作，以将所述电路操作为四种逻辑运行模式之一，即 “PASS”，“LEFT”，“CROSS”或“RIGHT”模式或两种非逻辑模式之一，即“隔离”或“透明”模式，或在本文上述模式的组合的任何子集中。以及用于组装多个TLC电路以执行阵列状结构中的逻辑功能的方法。

32. 发明授权

US06181164B2 Linear feedback shift register in a programmable gate array 有权
标题翻译：可编程门阵列中的线性反馈移位寄存器
公开(公告)号：US06181164B2
公开(公告)日：2001-01-30
申请号：US09312369
申请日：1999-05-13
申请人： Andrew J. Miller
发明人： Andrew J. Miller
IPC分类号： H03K19173
CPC分类号： H03K19/1736
摘要： A linear feedback shift register in a programmable gate array. A first lookup table is configured as a shift register having n selectable taps and a shift-input. A second lookup table is configured as a parity generator and has inputs coupled to the n selectable taps and an output coupled to the shift-input of the shift register.
摘要翻译：可编程门阵列中的线性反馈移位寄存器。第一查找表被配置为具有n个可选抽头和移位输入的移位寄存器。第二查找表被配置为奇偶校验发生器并且具有耦合到n个可选抽头的输入和耦合到移位寄存器的移位输入的输出。

33. 发明授权

US5923185A Logic circuit programmable to implement at least two logic functions 失效
标题翻译：逻辑电路可编程实现至少两个逻辑功能
公开(公告)号：US5923185A
公开(公告)日：1999-07-13
申请号：US815095
申请日：1997-03-12
申请人： Shi-dong Zhou
发明人： Shi-dong Zhou
IPC分类号： H03K19/173 , H03K19/094
CPC分类号： H03K19/1736
摘要： The present invention provides a logic circuit that is programmable to implement a first logic function or a second logic function using as few as four transistors. In one embodiment, the logic circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first signal line for receiving a first input signal, a second signal line for receiving a second input signal, a control signal line for receiving a control signal, and an output signal line for receiving an output signal. The first transistor and the second transistor are connected in series between the control signal line and the output signal line. The third transistor is connected in series between the first input signal line and the output signal line. The fourth transistor is connected in series between the second input signal line and the output signal line. In addition, the first signal line is connected to the gates of the first and fourth transistors, and the second signal line is connected to the gates of the second and third transistors. The state of the control signal provided to the control signal line determines whether the logic circuit implements the first logic function or the second logic function. The first and second logic functions can be (1) an exclusive NOR function or an AND function; or (2) an OR function or an exclusive OR function.
摘要翻译：本发明提供一种可编程以使用至少四个晶体管实现第一逻辑功能或第二逻辑功能的逻辑电路。在一个实施例中，逻辑电路包括第一晶体管，第二晶体管，第三晶体管，第四晶体管，用于接收第一输入信号的第一信号线，用于接收第二输入信号的第二信号线，控制信号线用于接收控制信号，以及用于接收输出信号的输出信号线。第一晶体管和第二晶体管串联在控制信号线和输出信号线之间。第三晶体管串联连接在第一输入信号线和输出信号线之间。第四晶体管串联连接在第二输入信号线和输出信号线之间。此外，第一信号线连接到第一和第四晶体管的栅极，第二信号线连接到第二和第三晶体管的栅极。提供给控制信号线的控制信号的状态确定逻辑电路是否实现第一逻辑功能或第二逻辑功能。第一和第二逻辑功能可以是（1）独占的或非函数或AND函数; 或（2）OR函数或异或函数。

34. 发明授权

US5912572A Synchronizing clock pulse generator for logic derived clock signals with synchronous clock suspension capability for a programmable device 失效
标题翻译：同步时钟脉冲发生器用于可编程器件的同步时钟暂停功能的逻辑导出时钟信号
公开(公告)号：US5912572A
公开(公告)日：1999-06-15
申请号：US825359
申请日：1997-03-28
申请人： W. Alfred Graf, III
发明人： W. Alfred Graf, III
IPC分类号： H03K19/173 , H03L7/00 , H03K17/22
CPC分类号： H03K19/1736 , H03L7/00
摘要： A programmable device includes a circuit for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input logic signals from which the synchronized logic derived clock signal is created. Further, the programmable device includes circuit for suspending a clock signal. In one embodiment, an asynchronous logic derived clock signal is generated and synchronized with a synchronous clock signal provided to the programmable device to produce a synchronized logic derived clock signal. The synchronized logic derived clock signal is logically combined with the synchronous clock signal to produce a suspended clock signal.
摘要翻译：可编程器件包括用于从多个输入信号中的一个或多个产生异步逻辑导出时钟信号的电路。用于将异步逻辑导出的时钟信号同步到参考时钟信号的电路耦合到用于产生的电路。用于同步的电路从异步逻辑导出的时钟信号和参考时钟信号产生同步的逻辑导出时钟信号。同步逻辑导出时钟信号具有固定持续时间逻辑高间隔，用于可变持续时间逻辑高输入逻辑信号的高间隔，从其产生同步的逻辑导出时钟信号。此外，可编程器件包括用于暂停时钟信号的电路。在一个实施例中，异步逻辑导出时钟信号被产生并与提供给可编程器件的同步时钟信号同步，以产生同步的逻辑导出时钟信号。同步的逻辑导出时钟信号与同步时钟信号逻辑组合以产生一个挂起的时钟信号。

35. 发明授权

US5903165A Programmable logic array with a hierarchical routing resource 失效
标题翻译：具有分层路由资源的可编程逻辑阵列
公开(公告)号：US5903165A
公开(公告)日：1999-05-11
申请号：US253041
申请日：1994-06-02
申请人： Gareth James Jones , Gordon Stirling Work
发明人： Gareth James Jones , Gordon Stirling Work
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17704 , H03K19/1774 , H03K19/17744 , H03K19/17796
摘要： A configurable semi-conductor integrated circuit has an area thereof formed with a plurality of logic circuits at discrete sites or cells respectively defining a matrix array of cells. The matrix array of cells is subdivided at least into zones, each having a matrix array of cells, and further includes a porting arrangement for each zone; and a hierarchical routing resource structure including: (i) global connection paths having selectable connections with the porting arrangement of each zone and which extend continuously across more than one zone, (ii) medium connection paths extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and (iii) local direct connection paths having for each cell a restricted signal translation system between inputs and outputs of the cells and defining first and second sets of logic circuits.
摘要翻译：可配置的半导体集成电路具有在离散位置处形成有多个逻辑电路的区域或分别限定单元阵列阵列的单元。单元的矩阵阵列至少细分为各个区域，每个区域具有单元的矩阵阵列，并且还包括每个区域的移植装置; 以及分层路由资源结构，其包括：（i）全局连接路径，其具有与每个区域的移植布置的可选择连接，并且连续地跨多于一个区域延伸;（ii）从该移植装置延伸并且可选择地与第区域中的至少一些小区，以及（iii）对于每个小区的本地直接连接路径，在小区的输入和输出之间限定信号转换系统，并且定义第一和第二组逻辑电路。

36. 发明授权

US5889413A Lookup tables which double as shift registers 失效
标题翻译：查找表作为移位寄存器加倍
公开(公告)号：US5889413A
公开(公告)日：1999-03-30
申请号：US754421
申请日：1996-11-22
申请人： Trevor J. Bauer
发明人： Trevor J. Bauer
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： G11C19/00 , H03K19/1736 , H03K19/17728 , H03K19/17736 , H03K19/17768
摘要： A logic element for an FPGA which can be configured as any one of a random access memory, a shift register and a lookup table. The logic element includes a plurality of memory cells which are interconnected such that the data output of each cell can serve as the input to the next memory cell. Thus the logic element effectively functions as a shift register. Shift registers of arbitrary length can be created by using a lookup table address multiplexer to select any memory cell output (not necessarily the last memory cell output) of the lookup table, and by chaining lookup tables of plural logic elements in series.
摘要翻译：用于FPGA的逻辑元件，其可以被配置为随机存取存储器，移位寄存器和查找表中的任何一个。逻辑元件包括互连的多个存储器单元，使得每个单元的数据输出可以用作下一个存储器单元的输入。因此，逻辑元件有效地用作移位寄存器。可以通过使用查找表地址多路复用器来选择查找表的任何存储单元输出（不一定是最后的存储单元输出）以及通过串联链接多个逻辑元件的查找表来创建任意长度的移位寄存器。

37. 发明授权

US5844829A Configurable parallel and bit serial load apparatus 失效
公开(公告)号：US5844829A
公开(公告)日：1998-12-01
申请号：US985392
申请日：1997-12-04
申请人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
发明人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17748
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.

38. 发明授权

US5742531A Configurable parallel and bit serial load apparatus 失效
公开(公告)号：US5742531A
公开(公告)日：1998-04-21
申请号：US642758
申请日：1996-05-03
申请人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
发明人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17748
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.

39. 发明授权

US5734334A Programmable port for crossbar switch 失效
标题翻译：交叉开关可编程端口
公开(公告)号：US5734334A
公开(公告)日：1998-03-31
申请号：US516320
申请日：1995-08-17
申请人： Wen-Jai Hsieh , Chi-Song Horng , Chun Chiu Daniel Wong , Gerchih Chou , Shrikant Sathe , Kent Dahlgren
发明人： Wen-Jai Hsieh , Chi-Song Horng , Chun Chiu Daniel Wong , Gerchih Chou , Shrikant Sathe , Kent Dahlgren
IPC分类号： H03K19/173 , H04Q1/00
CPC分类号： H03K19/1736
摘要： An electronic crossbar switch employs a switch array for selectively routing digital and analog signals between its terminals. A separate port for each terminal provides a path for digital and analog signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal with or without an input direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal.
摘要翻译：电子交叉开关采用开关阵列，用于在其端子之间选择性地路由数字和模拟信号。每个端子的独立端口为数字和模拟信号流入和流出交换机提供了路径。每个端口可被配置为在三态控制信号的控制下具有或不具有三态缓冲器，以响应于时钟和时钟使能信号来选择性地锁存输入或输出信号，以及缓冲通过或者流过开关端子的信号，没有输入方向控制信号。为所有端口提供一组控制输入，允许外部主机与每个端口并行发送控制信号。每个端口可以被编程为选择其任何控制输入作为其三态，时钟使能，时钟或方向控制信号。

40. 发明授权

US5670896A High speed product term assignment for output enable, clock, inversion and set/reset in a programmable logic device 失效
标题翻译：用于可编程逻辑器件中的输出使能，时钟，反相和置位/复位的高速产品术语分配
公开(公告)号：US5670896A
公开(公告)日：1997-09-23
申请号：US533890
申请日：1995-09-26
申请人： Sholeh Diba , Wei-Yi Ku
发明人： Sholeh Diba , Wei-Yi Ku
IPC分类号： H03K19/173 , H03K7/38
CPC分类号： H03K19/1736
摘要： A macrocell for a programmable logic device includes private product term assignments to provide various functions including set and reset, output enable, clocking, and inversion. Each of these additional functions is provided by assigning one of the product terms associated with the macrocell to perform one of these functions locally. By means of additional logic circuitry these functions are achieved either singly or in combination for a particular macrocell, thus improving macrocell flexibility and in some cases conserving pins of the chip of which the programmable logic array is a part.
摘要翻译：用于可编程逻辑器件的宏单元包括专用产品项分配，以提供包括置位和复位，输出使能，时钟和反相等各种功能。这些附加功能中的每一个通过分配与宏单元相关联的产品项之一来提供，以在本地执行这些功能之一。通过额外的逻辑电路，这些功能可以单独实现，也可以组合实现特定的宏单元，从而提高了宏单元的灵活性，并且在某些情况下节省了可编程逻辑阵列作为其一部分的芯片引脚。

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