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31. 发明申请

US20100123705A1 OPERATIONAL AMPLIFIER AND DISPLAY PANEL DRIVING DEVICE 有权
标题翻译：操作放大器和显示面板驱动装置
公开(公告)号：US20100123705A1
公开(公告)日：2010-05-20
申请号：US12620380
申请日：2009-11-17
申请人： Manabu Nishimizu , Atsushi Hirama , Koji Higuchi
发明人： Manabu Nishimizu , Atsushi Hirama , Koji Higuchi
IPC分类号： G09G5/00
CPC分类号： G09G3/3614 , G09G3/3666 , G09G3/3688 , G09G2300/0408 , H03F3/45183 , H03F2200/414 , H03F2203/45352 , H03F2203/45366 , H03F2203/45614 , H03F2203/45648
摘要： An operational amplifier includes an output circuit and a differential circuit. The output circuit outputs a voltage in a voltage range determined either from a highest voltage that is an upper limit of a predetermined power source range, or from a lowest voltage that is a lower limit of the predetermined power source range, to an intermediate voltage that is a voltage between the highest voltage and the lowest voltage. The differential circuit includes a first MOS transistor to which a driving signal for driving a display panel is input and a second MOS transistor to which a given input signal is input. The first MOS transistor and the second MOS transistor are connected in parallel, and a differential input-permissible-range of the differential circuit is wider than the voltage range of the output circuit.
摘要翻译：运算放大器包括输出电路和差分电路。输出电路输出在从作为规定电源范围的上限的最高电压或作为规定的电源范围的下限的最低电压决定的电压范围内的电压，是最高电压和最低电压之间的电压。差分电路包括输入用于驱动显示面板的驱动信号的第一MOS晶体管和输入给定输入信号的第二MOS晶体管。第一MOS晶体管和第二MOS晶体管并联连接，差分电路的差分输入允许范围比输出电路的电压范围宽。

32. 发明申请

US20100060324A1 VOLTAGE/CURRENT CONVERSION CIRCUIT 失效
标题翻译：电压/电流转换电路
公开(公告)号：US20100060324A1
公开(公告)日：2010-03-11
申请号：US12555551
申请日：2009-09-08
申请人： Toshiyuki ETOU
发明人： Toshiyuki ETOU
IPC分类号： H02M11/00
CPC分类号： G11C27/026 , H03F3/45475 , H03F2203/45136 , H03F2203/45511 , H03F2203/45512 , H03F2203/45528 , H03F2203/45534 , H03F2203/45536 , H03F2203/45562 , H03F2203/45594 , H03F2203/45614 , H03F2203/45616 , H03F2203/45618
摘要： Provided is voltage/current conversion circuit including: first and second capacitors; first and second resistors each connected to input terminal; first and second current sources; third and fourth resistors connected to current sources; differential amplifier for controlling the current sources; control unit for performing control, in first state, the input terminal is connected to the first and second capacitors; one input of the differential amplifier is connected to the first resistor and output of the first current source; the other input of the differential amplifier is connected to the second resistor and output of the second current source, and in second state, the second capacitor is connected between the output of the first current source and the one input of the differential amplifier, the first capacitor is connected between the output of the second current source and the other input of the differential amplifier.
摘要翻译：提供的电压/电流转换电路包括：第一和第二电容器; 第一和第二电阻器各自连接到输入端子; 第一和第二电流源; 连接到电流源的第三和第四电阻; 用于控制电流源的差分放大器; 用于执行控制的控制单元，在第一状态下，所述输入端子连接到所述第一和第二电容器; 差分放大器的一个输入端连接到第一电阻器和第一电流源的输出端; 差分放大器的另一输入端连接到第二电阻器和第二电流源的输出端，而在第二状态下，第二电容器连接在第一电流源的输出端和差分放大器的一个输入端之间，电容器连接在第二电流源的输出端和差分放大器的另一个输入端之间。

33. 发明申请

US20070222509A1 Amplifier circuit 有权
标题翻译：放大器电路
公开(公告)号：US20070222509A1
公开(公告)日：2007-09-27
申请号：US11703026
申请日：2007-02-06
申请人： Hirokazu Yoshizawa , Ryoichi Anzai , Toshiyuki Uchida , Akira Takeda , Minoru Ariyama , Atsushi Igarashi
发明人： Hirokazu Yoshizawa , Ryoichi Anzai , Toshiyuki Uchida , Akira Takeda , Minoru Ariyama , Atsushi Igarashi
IPC分类号： H03F1/14
CPC分类号： H03F1/3211 , H03F3/387 , H03F3/45475 , H03F3/45986 , H03F3/45995 , H03F2203/45138 , H03F2203/45212 , H03F2203/45614 , H03F2203/45616 , H03F2203/45681 , H03F2203/45726
摘要： Provided is a chopper amplifier circuit capable of eliminating an influence of a slew rate of an amplifier and suppressing spike generation to thereby obtain an output signal having little harmonic distortion. The chopper amplifier circuit according to the present invention includes: a first chopper circuit for chopping an input signal by a first pulse and a second pulse shifted from each other in phase by a half cycle, switching a relation of connection between an input terminal pair and an output terminal pair at a timing of the chopping, and outputting the input signal as a modulated signal; an amplifier for amplifying the modulated signal and outputting the modulated signal thus amplified as an amplified signal; a first sample hold circuit for holding the amplified signal at the first pulse and outputting the amplified signal at the second pulse; and a second sample hold circuit for holding the amplified signal at the second pulse and outputting the amplified signal at the first pulse.
摘要翻译：提供了能够消除放大器的转换速率的影响并抑制尖峰发生从而获得具有很小的谐波失真的输出信号的斩波放大器电路。根据本发明的斩波放大器电路包括：第一斩波电路，用于通过第一脉冲斩波输入信号和相位偏移半个周期的第二脉冲，切换输入端子对和在斩波的定时输出端子对，并输出该输入信号作为调制信号; 放大器，用于放大经调制的信号并输出被放大的被调制信号作为放大信号; 第一采样保持电路，用于保持放大的信号处于第一脉冲，并以第二脉冲输出放大的信号; 以及第二采样保持电路，用于将放大的信号保持在第二脉冲，并以第一脉冲输出放大的信号。

34. 发明授权

US09813040B2 Resistor attenuator with switch distortion cancellation 有权
公开(公告)号：US09813040B2
公开(公告)日：2017-11-07
申请号：US14857815
申请日：2015-09-17
申请人： Texas Instruments Incorporated
发明人： Rajendrakumar Joish
IPC分类号： H01P1/22 , H03H7/24 , H03F1/56 , H03F1/32 , H03F3/45
CPC分类号： H03H7/24 , H01P1/22 , H03F1/3211 , H03F1/56 , H03F3/45 , H03F3/45475 , H03F2203/45151 , H03F2203/45594 , H03F2203/45614 , H03F2203/45616
摘要： A programmable (multistep) resistor attenuator architecture (such as for input to a differential amplifier) provides cancellation for harmonic distortion currents. An attenuation node is coupled: (a) to an input node through R; (b) to a virtual ground through kR and a virtual ground switch Swf with on-resistance Rswf; and (c) to a differential ground through mR and a differential ground switch Swp with on-resistance Rswp. Swp can be sized relative to Swf such that a component Ipnf of Ipn through Rswp and mR to the attenuation node, and branching into kR and Rswf, matches (phase/magnitude), a harmonic current Ifn from the virtual ground through Rswf and kR to the attenuation node. Harmonic distortion cancelation at the virtual ground can be based on matching switches Swf and Swp and the resistors R, mR, kR, reducing sensitivity to PVT variations, input frequency and amplitude. The attenuator architecture is extendable to multistage configurations.

35. 发明授权

US09723405B2 Attenuating an input signal 有权
公开(公告)号：US09723405B2
公开(公告)日：2017-08-01
申请号：US15246373
申请日：2016-08-24
申请人： Red Lion 49 Limited
发明人： David Joseph Mate
IPC分类号： H04R3/04 , H03F3/45 , H03F3/187 , H03G1/00 , H03H11/24
CPC分类号： H04R3/04 , H03F3/187 , H03F3/45071 , H03F3/45475 , H03F2200/03 , H03F2200/165 , H03F2200/321 , H03F2203/45576 , H03F2203/45614 , H03G1/0005 , H03G1/0088 , H03G2201/106 , H03H11/245
摘要： Apparatus (301) for switchable attenuation of a differential input signal from a microphone includes positive and negative non-attenuating paths (406, 410) have n- and p-type MOSFETs (421, 422, 423, 424) in back-to-back configurations; positive and negative attenuating paths (405, 409) have n- and p-type MOSFETs (415, 416, 418, 419) in back-to-back configurations in combination with resistors; a gate driver (425) applies a drive signal of one polarity (QNEG) to gates of the n-type MOSFETs in the attenuating paths and the p-type MOSFETs in the non-attenuating paths, and a drive signal of opposite polarity (QPOS) to the gates of the p-type MOSFETs in the attenuating paths and the n-type MOSFETs in the non-attenuating paths; and the state of the MOSFETs depends on the drive signals at their gates, and thus the input signal may be routed via either the non-attenuating paths or the attenuating paths by controlling the drive signals.

36. 发明申请

US20170054415A1 DIFFERENTIAL VOLTAGE REFERENCE BUFFER WITH RESISTOR CHOPPING 审中-公开
标题翻译：具有电阻斩波的差分电压参考缓冲器
公开(公告)号：US20170054415A1
公开(公告)日：2017-02-23
申请号：US14830584
申请日：2015-08-19
申请人： QUALCOMM Incorporated
发明人： Dongyang Tang , Vijayakumar Dhanasekaran
IPC分类号： H03F1/26 , H03F3/45 , H03F3/387
CPC分类号： H03F1/26 , H03F1/086 , H03F1/342 , H03F3/187 , H03F3/387 , H03F3/393 , H03F3/45071 , H03F3/45475 , H03F2200/129 , H03F2200/156 , H03F2200/159 , H03F2200/21 , H03F2200/252 , H03F2200/372 , H03F2200/81 , H03F2200/87 , H03F2200/91 , H03F2203/45116 , H03F2203/45134 , H03F2203/45136 , H03F2203/45151 , H03F2203/45221 , H03F2203/45528 , H03F2203/45534 , H03F2203/45562 , H03F2203/45594 , H03F2203/45601 , H03F2203/45614 , H03F2203/45616
摘要： A voltage reference buffer circuit, including: an amplifier having input terminals and output terminals; a plurality of current sources coupled to the input terminals of the amplifier, the plurality of current sources including a plurality of degeneration resistors coupled to a first plurality of voltage supplies; and a degeneration resistor chopping module comprising a first and second plurality of switches coupled to the plurality of degeneration resistors.
摘要翻译：一种电压参考缓冲电路，包括：具有输入端和输出端的放大器; 耦合到放大器的输入端的多个电流源，所述多个电流源包括耦合到第一多个电压源的多个退化电阻; 以及退化电阻斩波模块，包括耦合到所述多个退化电阻器的第一和第二多个开关。

37. 发明授权

US09543907B2 Current-voltage conversion amplifier circuit including multiplier with a current offset removal unit and multi input amplifier 有权
标题翻译：电流 - 电压转换放大器电路包括具有电流偏移去除单元和多输入放大器的乘法器
公开(公告)号：US09543907B2
公开(公告)日：2017-01-10
申请号：US14605877
申请日：2015-01-26
申请人： Electronics and Telecommunications Research Institute
发明人： Young-deuk Jeon , Jung Hee Suk , Chun-Gi Lyuh , Yi-Gyeong Kim , Jong Pil Im , Min-Hyung Cho
IPC分类号： H03F3/08 , H03G3/00 , H03F3/45 , H03M1/12
CPC分类号： H03F3/082 , H03F3/087 , H03F3/45475 , H03F2203/45088 , H03F2203/45514 , H03F2203/45551 , H03F2203/45614 , H03G3/008 , H03M1/121
摘要： Provided is a current-voltage conversion amplifier circuit including: a plurality of light receiving devices generating a current signal proportional to an amount of light by receiving the light; multipliers amplifying the current signal, converting the amplified current signal into a first voltage signal, outputting the amplified current signal, or outputting the converted first voltage signal; multi input amplifiers outputting first and second output voltage pairs through a process for receiving output values of multipliers and an offset voltage and amplifying the received output values and offset voltage; a multiplexing unit selecting and outputting one first and second output voltage pair among the first and second output voltage pairs outputted from multi input amplifiers; and a signal conversion unit converting a difference value between first and second output voltages outputted from the multiplexing unit and outputting the converted digital signal.
摘要翻译：提供了一种电流 - 电压转换放大器电路，包括：多个光接收装置，通过接收光产生与光量成比例的电流信号; 放大电流信号的乘法器，将放大的电流信号转换成第一电压信号，输出放大的电流信号或输出转换的第一电压信号; 多输入放大器，通过用于接收乘法器的输出值和偏移电压的过程输出第一和第二输出电压对，并放大所接收的输出值和失调电压; 多路复用单元，从多输入放大器输出的第一和第二输出电压对中选择并输出一个第一和第二输出电压对; 以及信号转换单元，转换从多路复用单元输出的第一和第二输出电压之间的差值，并输出转换的数字信号。

38. 发明申请

US20160233874A1 Cross-Coupled Input Voltage Sampling and Driver Amplifier Flicker Noise Cancellation in a Switched Capacitor Analog-to-Digital Converter 有权
标题翻译：交叉耦合输入电压采样和驱动器放大器开关电容模数转换器中的闪烁噪声消除
公开(公告)号：US20160233874A1
公开(公告)日：2016-08-11
申请号：US14615001
申请日：2015-02-05
申请人： Infineon Technologies AG
发明人： Snezana Stojanovic , Patrizia Greco , Elmar Bach
IPC分类号： H03M1/08 , H03M3/00 , H03M1/12 , H03K17/10
CPC分类号： H03K17/10 , H03F1/26 , H03F3/45475 , H03F2203/45614 , H03M1/0836 , H03M1/089 , H03M1/1245 , H03M3/368 , H03M3/372 , H03M3/458
摘要： A switching component comprises a plurality of switches configured to receive a differential signal at an input and is configured to provide a non-inverted version of the differential signal at an output during a first phase of operation and an inverted version of the differential signal at an output during a second phase of operation. A driver amplifier component is configured to receive the non-inverted version of the differential signal at an input during the first phase of operation and the inverted version of the differential signal at an input during the second phase of operation. A sampling capacitor component is configured to sample the output of the driver amplifier component during the first phase of operation and the second phase of operation.
摘要翻译：开关部件包括多个开关，其被配置为在输入处接收差分信号，并且被配置为在第一操作阶段期间的输出处提供差分信号的非反相形式，并且在第在第二阶段的操作期间输出。驱动器放大器组件被配置为在第一操作阶段的输入处接收差分信号的非反相版本，并且在第二操作阶段在输入处接收差分信号的反相版本。采样电容器组件被配置为在第一操作阶段和第二阶段操作期间对驱动器放大器组件的输出进行采样。

39. 发明申请

US20160079949A1 RESISTOR ATTENUATOR WITH SWITCH DISTORTION CANCELLATION 有权
标题翻译：电阻衰减器与开关失灵消除
公开(公告)号：US20160079949A1
公开(公告)日：2016-03-17
申请号：US14857815
申请日：2015-09-17
申请人： Texas Instruments Incorporated
发明人： Rajendrakumar Joish
IPC分类号： H03H7/24 , H03F1/56 , H03F3/45
CPC分类号： H03H7/24 , H01P1/22 , H03F1/3211 , H03F1/56 , H03F3/45 , H03F3/45475 , H03F2203/45151 , H03F2203/45594 , H03F2203/45614 , H03F2203/45616
摘要： A programmable (multistep) resistor attenuator includes distortion cancellation for harmonic distortion currents. The attenuator includes at last one attenuation stage coupled between a signal input node and a virtual ground node (such as an input to a differential amplifier). The attenuation node is: (a) coupled to the input node through a resistor R; (b) coupled to the virtual ground node through a resistor kR and a virtual ground switch Swf with an on resistance Rswf; and (c) coupled to a differential ground through a resistor mR and a differential ground switch Swp with an on resistance Rswp. Swp is sized relative to Swf such that, when both Swp and Swf are conducting, a component Ipnf of a current Ipn through Rswp and mR to the attenuation node and branching into kR and Rswf, matches, in phase and magnitude, a harmonic current Ifn from the virtual ground through Rswf and kR to the attenuation node, thereby substantially canceling the harmonic distortion appearing at the virtual ground. Distortion cancellation can be based on cancellation is based on matching switches Swf and Swp and the resistors R, mR, kR, and hence is insensitive to PVT variations, input frequency and amplitude. an optimum ratio of Rswp and Rswf is a function of only a ratio of resistors, and hence is insensitive to values of Rswp and Rswf. The attenuator architecture is extendable to multistage configurations.
摘要翻译：可编程（多步）电阻衰减器包括谐波失真电流的失真消除。衰减器包括最后一个耦合在信号输入节点和虚拟接地节点（诸如差分放大器的输入）之间的衰减级。衰减节点为：（a）通过电阻R耦合到输入节点; （b）通过电阻kR和具有导通电阻Rswf的虚拟接地开关Swf耦合到虚拟接地节点; 和（c）通过电阻mR和具有导通电阻Rswp的差分接地开关Swp耦合到差动接地。 Swp的尺寸相对于Swf，使得当Swp和Swf都导通时，通过Rswp和mR的衰减节点的电流Ipn和分支到kR和Rswf的分量Ipnf在相位和幅度上匹配谐波电流Ifn 从虚拟地通过Rswf和kR到衰减节点，从而基本上消除出现在虚拟地面处的谐波失真。失真消除可以基于匹配开关Swf和Swp以及电阻R，mR，kR的抵消，因此对PVT变化，输入频率和幅度不敏感。 Rswp和Rswf的最佳比值仅是电阻比的函数，因此对Rswp和Rswf的值不敏感。衰减器架构可扩展到多级配置。

40. 发明申请

US20160079924A1 BIAS CIRCUIT, OPERATIONAL AMPLIFIER, AND DELTA SIGMA TYPE AD CONVERTER 审中-公开
标题翻译：偏置电路，运算放大器和DELTA SIGMA型AD转换器
公开(公告)号：US20160079924A1
公开(公告)日：2016-03-17
申请号：US14645325
申请日：2015-03-11
申请人： Kabushiki Kaisha Toshiba
发明人： Yosuke Ogawa , Shigeo Imai , Shinji Nakatsuka
IPC分类号： H03F1/02 , H03M3/00 , H03F3/45
CPC分类号： H03M3/422 , H03F1/0261 , H03F3/393 , H03F3/45183 , H03F3/45475 , H03F2203/45154 , H03F2203/45171 , H03F2203/45244 , H03F2203/45614 , H03M3/43 , H03M3/458
摘要： According to one embodiment, there are provided a bias voltage generation circuit that generates a bias voltage in an operational amplifier according to a bias current generated inside, and an adaptive timing control circuit that temporarily increases the bias current at a timing at which a first control signal configured to control an input signal of the operational amplifier changes in level.
摘要翻译：根据一个实施例，提供了一种偏置电压产生电路，其根据内部产生的偏置电流在运算放大器中产生偏置电压，以及自适应定时控制电路，其在第一控制的定时临时增加偏置电流配置为控制运算放大器的输入信号的信号电平变化。

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