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31. 发明授权

US07613943B2 Programmable system on a chip 有权
公开(公告)号：US07613943B2
公开(公告)日：2009-11-03
申请号：US11931772
申请日：2007-10-31
申请人： Greg Bakker , Khaled El-Ayat , Theodore Speers , Limin Zhu , Brian Schubert , Rabindranath Balasubramanian , Kurt Kolkind , Thomas Barraza , Venkatesh Narayanan , John McCollum , William C. Plants
发明人： Greg Bakker , Khaled El-Ayat , Theodore Speers , Limin Zhu , Brian Schubert , Rabindranath Balasubramanian , Kurt Kolkind , Thomas Barraza , Venkatesh Narayanan , John McCollum , William C. Plants
IPC分类号： H03K19/173 , G06F1/30
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

32. 发明授权

US07612614B2 Device and method for biasing a transistor amplifier 失效
公开(公告)号：US07612614B2
公开(公告)日：2009-11-03
申请号：US12416538
申请日：2009-04-01
申请人： Ping Wai Li , Cong Ke Li , Wei Wang
发明人： Ping Wai Li , Cong Ke Li , Wei Wang
IPC分类号： H03F3/04
CPC分类号： H03F1/30 , H03F3/45475 , H03F2200/213 , H03F2203/45136 , H03F2203/45244 , H03F2203/45622 , H03H7/0107 , H03H7/0153 , H03H11/1291
摘要： Provided is circuitry for biasing a transistor amplifier with a DC-voltage signal, the transistor amplifier having a first input terminal, a second input terminal, and an output terminal coupled to the second input terminal. The circuitry includes a sensor capacitor connected to the first input terminal and an impedance transistor arranged in parallel with said capacitor, the transistor and capacitor forming a low-pass filter. The circuitry also includes a biasing circuit configured to controllably vary a DC-voltage signal for operatively biasing the amplifier, the biasing circuit including a cascaded current arrangement configured to subdivide a reference current into smaller currents for selectively generating voltage potentials for biasing the impedance transistor to adjustably filter a noise component of the DC-voltage signal via the low-pass filter before the DC-voltage signal is provided to the first input terminal.

33. 发明授权

US07605659B2 Gain adjustment for programmable gain amplifiers 有权
标题翻译：可编程增益放大器的增益调整
公开(公告)号：US07605659B2
公开(公告)日：2009-10-20
申请号：US11753416
申请日：2007-05-24
申请人： Rodney Alan Hughes
发明人： Rodney Alan Hughes
IPC分类号： H03G3/00
CPC分类号： H03G1/0088 , H03F3/45475 , H03F2203/45136 , H03F2203/45522 , H03F2203/45526 , H03F2203/45534
摘要： A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.
摘要翻译：可编程增益放大器（PGA）电路包括都被耦合到放大器的输出的增益调整电路和增益选择电路。增益选择电路完成对放大器的反馈，同时增益调整电路被设置为提升或削减增益选择电路的增益。增益调整电路可以被布置为对PGA电路的总体增益的修整调整，其中可以将不同的调整调整映射到诸如查找表的每个增益设置。在其他示例实现中，PGA电路可以使用调制方案周期性地在多个增益设置之间切换，使得总体增益根据占空比，脉冲宽度或Δ-Σ调制在各种增益设置之间进行混合，具有时间对PGA电路整体增益的平均效应。

34. 发明申请

US20090212830A1 BUFFER DEVICE FOR SWITCHED CAPACITANCE CIRCUIT 有权
标题翻译：用于开关电容电路的缓冲器装置
公开(公告)号：US20090212830A1
公开(公告)日：2009-08-27
申请号：US12391574
申请日：2009-02-24
申请人： Marco Zamprogno , Germano Nicollini , Alberto Minuti
发明人： Marco Zamprogno , Germano Nicollini , Alberto Minuti
IPC分类号： H03K3/00
CPC分类号： H03F1/3211 , H03F3/005 , H03F3/45475 , H03F3/45977 , H03F2203/45101 , H03F2203/45136 , H03F2203/45212 , H03F2203/45514
摘要： An integrated buffer device for a switched capacitance circuit having a buffer with an output for an output voltage dependent upon an input voltage that can be supplied by a source to the buffer device; a capacitive switching component that can be switched between a first and second condition and connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; the capacitive switching component provided with a terminal having an associated stray capacitance; a charging and discharging device configured to pre-charge the stray capacitance at a reference voltage before taking up the second condition and to pre-discharge the stray capacitance before taking up the first condition.
摘要翻译：一种用于开关电容电路的集成缓冲装置，具有缓冲器，该缓冲器具有取决于可由缓冲装置提供的输入电压的输出电压的输出; 电容开关部件，其可以在第一和第二状态之间切换并分别连接到源极和缓冲器，以将输入电压传递到输出端; 所述电容开关元件设置有具有相关杂散电容的端子; 充电和放电装置，其被配置为在占用所述第二状态之前以参考电压对所述寄生电容进行预充电，并且在占用所述第一状态之前对所述杂散电容进行预放电。

35. 发明申请

US20090207063A1 VARIABLE PASSIVE COMPONENTS WITH HIGH RESOLUTION VALUE SELECTION AND CONTROL 失效
标题翻译：具有高分辨率选择和控制的可变被动组件
公开(公告)号：US20090207063A1
公开(公告)日：2009-08-20
申请号：US12431581
申请日：2009-04-28
申请人： ROBERT D. WASHBURN , Robert F. McClanahan
发明人： ROBERT D. WASHBURN , Robert F. McClanahan
IPC分类号： H03M1/66
CPC分类号： H03H7/25 , H03F1/08 , H03F1/3211 , H03F1/56 , H03F3/343 , H03F3/4508 , H03F3/45475 , H03F2200/222 , H03F2200/321 , H03F2200/387 , H03F2200/91 , H03F2203/45031 , H03F2203/45136 , H03F2203/45352 , H03H7/40 , H03H11/30 , H03H11/48 , H03H11/481 , H03H11/53
摘要： The present system provides a method for varying the value of passive components in electronic circuits. Passive components can range from basic resistors, capacitors, and inductors to complex, structures such as transmission lines and resonant cavities. Value selection and variation can either be dynamically performed during circuit operation or as a one-time part of the manufacturing process as determined by the requirements of the specific application. A digital-to-analog converter (DAC) circuit is used to input value selection data digitally, and control value selection with value resolution dependent on the resolution of the DAC. An alternate embodiment is provided for high frequency operation.
摘要翻译：本系统提供了一种改变电子电路中无源元件的值的方法。无源元件可以从基本的电阻器，电容器和电感器到复杂的结构，如传输线和谐振腔。价值选择和变化可以在电路运行期间动态执行，也可以作为制造过程的一次性部分，由特定应用的要求确定。数模转换器（DAC）电路用于数字输入值选择数据，并根据DAC的分辨率根据值分辨率进行控制值选择。提供了用于高频操作的替代实施例。

36. 发明授权

US07560952B2 Integrated circuit device having state-saving and initialization feature 有权
标题翻译：具有省电和初始化功能的集成电路装置
公开(公告)号：US07560952B2
公开(公告)日：2009-07-14
申请号：US12028615
申请日：2008-02-08
申请人： Limin Zhu , Theodore Speers , Gregory Bakker
发明人： Limin Zhu , Theodore Speers , Gregory Bakker
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： An integrated circuit device has a state-saving feature and includes a programmable logic block, I/O pads, a dedicated register, at least one volatile memory block, a non-volatile memory block, a condition-sensing circuit for detecting at least one condition, A control circuit such as a state machine controls the saving of states of various volatile memories and registers to the non-volatile memory and also controls the initialization of the volatile registers and memories using the saved state data.
摘要翻译：集成电路装置具有省电特征，并且包括可编程逻辑块，I / O焊盘，专用寄存器，至少一个易失性存储器块，非易失性存储器块，用于检测至少一个条件，诸如状态机的控制电路控制各种易失性存储器和寄存器的状态的保存到非易失性存储器，并且还使用保存的状态数据来控制易失性寄存器和存储器的初始化。

37. 发明申请

US20090161890A1 MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) CAPACITIVE SENSING CIRCUIT 有权
标题翻译：微电子机械系统（MEMS）电容式感应电路
公开(公告)号：US20090161890A1
公开(公告)日：2009-06-25
申请号：US12014697
申请日：2008-01-15
申请人： Yuh-Min LIN
发明人： Yuh-Min LIN
IPC分类号： H04R3/00
CPC分类号： H03F3/187 , H03F3/45475 , H03F2200/03 , H03F2203/45136 , H03F2203/45544 , H03F2203/45604 , H04R19/04
摘要： The present invention discloses a Micro-Electro-Mechanical Systems (MEMS) capacitive sensing circuit wherein two input nodes of a fully differential amplifier are separately connected to a MEMS capacitive sensing device and a matching capacitor, which both contain similar capacity value and connect to a bias node, and two resistors separately connect the MEMS capacitive sensing device and the matching capacitor to ground (zero voltage). Thus, the present invention could effectively eliminate the bias noise in the circuit without any discrete capacitor and capable for designer to integrate all circuit devices into an IC.
摘要翻译：本发明公开了一种微电子机械系统（MEMS）电容感测电路，其中全差分放大器的两个输入节点分别连接到MEMS电容感测装置和匹配电容器，它们都具有类似的容量值并连接到偏置节点和两个电阻将MEMS电容感测器件和匹配电容器分别连接到地（零电压）。因此，本发明可以有效地消除电路中的偏置噪声，而无需任何分立电容器，并且能够将所有电路器件集成到IC中。

38. 发明申请

US20090161275A1 INTEGRATED CONTROLLING CHIP 审中-公开
标题翻译：集成控制芯片
公开(公告)号：US20090161275A1
公开(公告)日：2009-06-25
申请号：US12122719
申请日：2008-05-18
申请人： Kun-Tai Wu , Chin-Chieh Chao , Ching-Ching Chi
发明人： Kun-Tai Wu , Chin-Chieh Chao , Ching-Ching Chi
IPC分类号： H02H3/20
CPC分类号： H03F3/45475 , H01L27/0251 , H03F1/52 , H03F2200/444 , H03F2203/45136 , H03F2203/45594
摘要： An integrated controlling chip includes a signal processing unit, a resistance unit and an electrostatic discharge protection circuit. The signal processing unit includes an input port. The resistance unit includes a first node coupled to a signal pin of the integrated controlling chip, and includes a second node coupled to the input port of the signal processing unit. The electrostatic discharge protection circuit includes a node coupled between the first node of the resistance unit and the signal pin of the integrated controlling chip.
摘要翻译：集成控制芯片包括信号处理单元，电阻单元和静电放电保护电路。信号处理单元包括输入端口。电阻单元包括耦合到集成控制芯片的信号引脚的第一节点，并且包括耦合到信号处理单元的输入端口的第二节点。静电放电保护电路包括耦合在电阻单元的第一节点和集成控制芯片的信号引脚之间的节点。

39. 发明授权

US07525380B2 Method and system for varying gain exponentially with respect to a control signal 有权
公开(公告)号：US07525380B2
公开(公告)日：2009-04-28
申请号：US11455983
申请日：2006-06-20
申请人： Christopher Yong
发明人： Christopher Yong
IPC分类号： H03F3/45
CPC分类号： H03F3/4508 , H03F3/3432 , H03F3/45475 , H03F2200/375 , H03F2200/393 , H03F2200/447 , H03F2200/453 , H03F2200/456 , H03F2203/45101 , H03F2203/45136 , H03G7/08
摘要： A method for varying gain exponentially with respect to a control signal is provided. The method includes receiving a primary control signal. A secondary control signal is generated based on the primary control signal. The secondary control signal is provided to a variable gain amplifier and is operable to exponentially vary a gain for the variable gain amplifier with respect to the primary control signal.

40. 发明授权

US07504882B2 Differential amplifier circuit and semiconductor device 失效
标题翻译：差分放大电路和半导体器件
公开(公告)号：US07504882B2
公开(公告)日：2009-03-17
申请号：US11510623
申请日：2006-08-28
申请人： Hirofumi Saito
发明人： Hirofumi Saito
IPC分类号： H03F3/45
CPC分类号： G11C7/067 , G11C7/08 , H03F3/3022 , H03F3/393 , H03F3/45192 , H03F3/45475 , H03F3/45775 , H03F2203/45136 , H03F2203/45212 , H03F2203/45512 , H03F2203/45548 , H03F2203/45588 , H03F2203/45616 , H03F2203/45681 , H03F2203/45726
摘要： A differential amplifier circuit in which an input offset voltage is very small. The differential amplifier circuit includes an input-stage differential amplifier section and a cascode-connected single-ended output section connected to the input-stage differential amplifier section. The input-stage differential amplifier section has a folded-cascode-connection. An inverted signal and non-inverted signal on the input side and output side, respectively, of the input-stage differential amplifier section are switched alternatingly in time-shared fashion by switches that are operated by two chopping clock signals of opposite phase.
摘要翻译：其中输入失调电压非常小的差分放大器电路。差分放大器电路包括输入级差分放大器部分和连接到输入级差分放大器部分的共源共栅型单端输出部分。输入级差分放大器部分具有折叠共源共栅连接。输入级差分放大器部分的输入侧和输出侧的反相信号和非反相信号通过由相反相位的两个斩波时钟信号操作的开关以时间共享的方式交替地切换。

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