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31. 发明申请

US20160013636A1 Area-Efficient Clamp for Power Ring ESD Protection Using a Transmission Gate 有权
标题翻译：使用传输门的电源环ESD保护区域高效钳位
公开(公告)号：US20160013636A1
公开(公告)日：2016-01-14
申请号：US14325559
申请日：2014-07-08
申请人： Hong Kong Applied Science & Technology Research Institute Company Limited
发明人： Xiaowu CAI , Beiping YAN , Xiao HUO
IPC分类号： H02H9/04
CPC分类号： H02H9/04 , H01L27/0285 , H02H9/046
摘要： Electrostatic discharge (ESD) protection is provided by a charge-latching power-to-ground clamp circuit. A filter capacitor and resistor generate a filter voltage that is buffered by three stages to drive the gate of a BigFET such as a large n-channel transistor. A transmission gate between the stages turns off when BigFET turns on, causing charge to be latched. The filter capacitor can then discharge while the BigFET remains on. A leaker resistor slowly discharges the gate of the large BigFET and turns the transmission gate back on when the BigFET turns off after shunting the ESD current. The length of time that the clamp shunts the ESD current is determined by the leaker resistor and gate capacitance of the BigFET, not by the filter capacitor, so a small filter capacitor may be used.
摘要翻译：静电放电（ESD）保护由充电闩锁电源对地钳位电路提供。滤波电容器和电阻器产生三级缓冲器的滤波电压，以驱动大型n沟道晶体管等BigFET的栅极。当BigFET导通时，两级之间的传输门关闭，导致电荷被锁存。然后，当BigFET保持导通时，滤波电容可以放电。漏电电阻缓慢放电大型BigFET的栅极，并在分流ESD电流后BigFET关断时将传输门重新打开。钳位分流ESD电流的时间长度由BigFET的漏电阻和栅极电容决定，而不是由滤波电容确定，因此可以使用小的滤波电容。

32. 发明授权

US09202808B2 Integrated circuit electrical protection device 有权
标题翻译：集成电路电气保护装置
公开(公告)号：US09202808B2
公开(公告)日：2015-12-01
申请号：US14231849
申请日：2014-04-01
申请人： Michael A. Stockinger , Wenzhong Zhang , Xu Zhang
发明人： Michael A. Stockinger , Wenzhong Zhang , Xu Zhang
IPC分类号： H01L27/02
CPC分类号： H01L27/0285 , H01L27/0274 , H01L29/1087 , H01L29/4238 , H01L29/78
摘要： An integrated circuit electrical protection device is disclosed that includes a semiconductor substrate and a plurality of transistor fingers partitioned into a plurality of segments. The segments are distinguished from one another by well-ties spaced apart from each other within a source/drain region that is shared by adjacent segments.
摘要翻译：公开了一种集成电路电气保护装置，其包括半导体衬底和划分成多个段的多个晶体管指状物。通过在由相邻段共享的源极/漏极区域内彼此间隔开的区域，这些区段彼此区分开。

33. 发明申请

US20150318275A1 ESD CLAMP CIRCUIT 有权
标题翻译： ESD钳位电路
公开(公告)号：US20150318275A1
公开(公告)日：2015-11-05
申请号：US14702356
申请日：2015-05-01
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Guang Chen , Huijuan Cheng , Hongwei Li
IPC分类号： H01L27/02
CPC分类号： H01L27/0285 , H01L27/0251 , H01L27/0266 , H01L27/0288
摘要： An ESD clamp circuit includes a power supply, a ground supply, an ESD detection transistor, a capacitor having a first terminal connected to the power supply and a second terminal connected to a gate of the ESD detection transistor, and a first resistor connected in series with the capacitor between the power and ground supplies. The ESD clamp circuit also includes a clamp transistor having a first terminal connected to the power supply and a second terminal connected to the ground terminal, an inverter having an input connected to a first terminal of the ESD detection transistor and an output connected to the gate of the clamp transistor, a feedback transistor connected across the inverter, and a second resistor having a first terminal connected to the gate of the clamp transistor and to a second terminal to the ground supply.
摘要翻译： ESD钳位电路包括电源，接地电源，ESD检测晶体管，具有连接到电源的第一端子的电容器和连接到ESD检测晶体管的栅极的第二端子以及串联连接的第一电阻器电容器与电源和地电源之间。 ESD钳位电路还包括具有连接到电源的第一端子和连接到接地端子的第二端子的钳位晶体管，具有连接到ESD检测晶体管的第一端子的输入端和连接到栅极的输出端的反相器钳位晶体管，跨过反相器连接的反馈晶体管，以及第二电阻器，其具有连接到钳位晶体管的栅极的第一端子和连接到地电源的第二端子。

34. 发明申请

US20150249079A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20150249079A1
公开(公告)日：2015-09-03
申请号：US14707510
申请日：2015-05-08
申请人： ROHM CO., LTD.
发明人： Kenji ARAI
IPC分类号： H01L27/02 , H01L23/522 , H01L23/50 , H03K5/1252
CPC分类号： H01L27/0288 , H01L23/50 , H01L23/5227 , H01L27/0266 , H01L27/0285 , H01L2924/0002 , H03K5/1252 , H01L2924/00
摘要： An input signal having a high level or a low level is input to a pad. A first protection element includes a first transistor configured as an N-channel MOSFET designed so as to withstand ESD. A second protection element includes a second transistor configured as a P-channel MOSFET designed so as to withstand ESD. A capacitance element is connected to a second line, and forms an RC filter together with a filter resistor. The capacitance element includes at least one from among a third transistor having the same device structure as that of the first transistor and a fourth transistor having the same device structure as that of the second transistor.
摘要翻译：具有高电平或低电平的输入信号被输入到焊盘。第一保护元件包括被配置为设计成能够承受ESD的N沟道MOSFET的第一晶体管。第二保护元件包括被配置为设计成能够承受ESD的P沟道MOSFET的第二晶体管。电容元件连接到第二线，并与滤波电阻一起形成RC滤波器。电容元件包括具有与第一晶体管相同的器件结构的第三晶体管中的至少一个晶体管和与第二晶体管具有相同器件结构的第四晶体管。

35. 发明授权

US09118180B2 Input protection circuit 有权
标题翻译：输入保护电路
公开(公告)号：US09118180B2
公开(公告)日：2015-08-25
申请号：US13782623
申请日：2013-03-01
申请人： YOKOGAWA ELECTRIC CORPORATION
发明人： Kazuhide Yasuda , Hiroaki Hagiwara
IPC分类号： H02H3/20 , H01L27/02 , H02H9/04
CPC分类号： H02H3/207 , H01L27/0285 , H02H9/046
摘要： An input protection circuit includes: a first transistor of a field-effect type coupled in series between an input terminal and an electronic circuit, the input terminal receiving an input voltage, the electronic circuit receiving an input voltage, the first transistor switching to an off-state in a case where the input voltage is higher than a positive power supply voltage of the electronic circuit; a second transistor of a field-effect type coupled in series between the first transistor and the electronic circuit, the second transistor switching to an off-state in a case where the input voltage is lower than the negative power supply voltage of the electronic circuit; and a voltage control circuit configured to maintain gate-source voltages of the first transistor and the second transistor as voltages within a power supply voltage range of the electronic circuit based on the input voltage.
摘要翻译：输入保护电路包括：串联耦合在输入端子和电子电路之间的场效应晶体管，输入端子接收输入电压，电子电路接收输入电压，第一晶体管切换到截止状态在输入电压高于电子电路的正电源电压的情况下，在第一晶体管和电子电路之间串联耦合的场效应晶体管的第二晶体管，在输入电压低于电子电路的负电源电压的情况下，第二晶体管切换到截止状态; 以及电压控制电路，被配置为基于所述输入电压将所述第一晶体管和所述第二晶体管的栅源电压保持在所述电子电路的电源电压范围内。

36. 发明申请

US20150229126A1 Semiconductor ESD Circuit and Method 审中-公开
标题翻译：半导体ESD电路及方法
公开(公告)号：US20150229126A1
公开(公告)日：2015-08-13
申请号：US14690739
申请日：2015-04-20
申请人： Infineon Technologies AG
发明人： Krzysztof Domanski , Wolfgang Soldner , Cornelius Christian Russ , David Alvarez , Adrien Ille
IPC分类号： H02H9/04
CPC分类号： H02H9/046 , H01L27/0285 , H01L29/0692 , H01L29/1083
摘要： In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
摘要翻译：在一个实施例中，用于在第一节点和第二节点之间提供保护的静电放电（ESD）电路包括具有耦合到第一节点的第一源极/漏极和耦合到中间节点的第二源极/漏极的第一MOS器件。 ESD电路还包括耦合在第一MOS器件的栅极和第一节点之间的第一电容器，耦合在第一MOS器件的中间节点的栅极之间的第一电阻器，第二MOS / 中间节点和耦合到第二节点的第二源极/漏极，耦合在第二MOS器件的栅极和第一节点之间的第二电容器，以及耦合在第二MOS器件的栅极和第二节点之间的第二电阻器。

37. 发明授权

US09076656B2 Electrostatic discharge (ESD) clamp circuit with high effective holding voltage 有权
标题翻译：具有高有效保持电压的静电放电（ESD）钳位电路
公开(公告)号：US09076656B2
公开(公告)日：2015-07-07
申请号：US13875618
申请日：2013-05-02
申请人： Freescale Semiconductor, Inc.
发明人： Melanie Etherton , Alex P. Gerdemann , James W. Miller , Mohamed S. Moosa , Robert S. Ruth , Michael A. Stockinger
IPC分类号： H01L27/02
CPC分类号： H01L27/0292 , H01L27/0285
摘要： Boosted Electrostatic Discharge (ESD) clamp circuit with high effective holding voltage. In some embodiments, an integrated circuit may include a trigger circuit operably coupled to a first voltage bus and to a reference bus; a diode including an anode terminal operably coupled to a second voltage bus, the second voltage bus distinct from the first voltage bus; a transistor including a gate operably coupled to an output terminal of the trigger circuit, a drain operably coupled to a cathode terminal of the diode, and a source operably coupled to the reference bus; and an input/output (I/O) cell operably coupled to the first voltage bus, the second voltage bus, and the reference bus.
摘要翻译：具有高有效保持电压的增压静电放电（ESD）钳位电路。在一些实施例中，集成电路可以包括可操作地耦合到第一电压总线和参考总线的触发电路; 二极管，包括可操作地耦合到第二电压总线的阳极端子，所述第二电压母线与所述第一电压总线不同; 晶体管，其包括可操作地耦合到触发电路的输出端的栅极，可操作地耦合到二极管的阴极端子的漏极和可操作地耦合到参考总线的源极; 以及可操作地耦合到第一电压总线，第二电压总线和参考总线的输入/输出（I / O）单元。

38. 发明申请

US20150171739A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20150171739A1
公开(公告)日：2015-06-18
申请号：US14632104
申请日：2015-02-26
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Koichiro KAMATA
IPC分类号： H02M1/32 , H02J17/00 , H02M7/217
CPC分类号： H02M1/32 , G06K19/0701 , G06K19/0715 , G06K19/07749 , H01L27/0248 , H01L27/0285 , H01L27/1225 , H02H9/046 , H02J7/025 , H02J17/00 , H02J50/12 , H02M7/217
摘要： To prevent damage on an element even when a voltage high enough to break the element is input. A semiconductor device of the invention operates with a first voltage and includes a protection circuit which changes the value of the first voltage when the absolute value of the first voltage is higher than a reference value. The protection circuit includes: a control signal generation circuit generating a second voltage based on the first voltage and outputting the generated second voltage; and a voltage control circuit. The voltage control circuit includes a transistor which has a source, a drain, and a gate, and which is turned on or off depending on the second voltage input to the gate and thus controls whether the value of the first voltage is changed based on the amount of current flowing between the source and the drain. The transistor also includes an oxide semiconductor layer.
摘要翻译：即使输入足够高的电压来破坏元件，也能防止元件的损坏。本发明的半导体器件以第一电压工作，并且包括当第一电压的绝对值高于参考值时改变第一电压的值的保护电路。所述保护电路包括：控制信号生成电路，其基于所述第一电压生成第二电压，并输出所生成的第二电压; 和电压控制电路。电压控制电路包括具有源极，漏极和栅极的晶体管，并且其根据输入到栅极的第二电压而导通或截止，从而基于第一电压的值是否改变第一电压的值在源极和漏极之间流动的电流量。晶体管还包括氧化物半导体层。

39. 发明申请

US20150115342A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20150115342A1
公开(公告)日：2015-04-30
申请号：US14517657
申请日：2014-10-17
申请人： Renesas Electronics Corporation
发明人： Yoshinori KAYA , Yasushi NAKAHARA , Azuma ARAYA , Ryo KANDA , Tomonobu KURIHARA , Tetsu TODA
IPC分类号： H01L27/06 , H01L29/06
CPC分类号： H02M1/088 , H01L27/0285 , H01L27/0292 , H01L27/0296 , H01L27/0629 , H01L27/0922 , H01L29/0642 , H01L29/0847 , H01L29/0878 , H01L29/1033 , H01L29/1079 , H01L29/405 , H01L29/42368 , H01L29/7816 , H01L29/7835 , H01L29/7838 , H03K2017/6875 , H03K2217/0081
摘要： Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other.
摘要翻译：提供了包括第一导电类型的衬底，第一电路区域，分离区域，第二电路区域和整流元件的半导体器件。整流元件具有第二导电类型层，第一高浓度第二导电类型区域，第二高浓度第二导电类型区域，元件隔离膜，第一绝缘层和第一导电膜。第一触点耦合到第一高浓度第二导电类型区域，第二触点耦合到第二高浓度第二导电类型区域。第三触点耦合到第一导电膜。第一触点，第二触点和第三触点彼此分离。

40. 发明授权

US08995101B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US08995101B2
公开(公告)日：2015-03-31
申请号：US13779464
申请日：2013-02-27
申请人： STMicroelectronics (Rousset) SAS
发明人： Nicolas Demange
IPC分类号： H02H9/04 , H01L27/02
CPC分类号： H02H9/046 , H01L27/0285 , H02H9/041 , H02H9/043
摘要： An electrostatic discharge protection circuit is coupled to a power supply rail and a ground supply rail of an integrated circuit and includes at least one shunt configured to couple the supply rails and a trigger configured to supply on an output a shunt control voltage to a control terminal of the shunt to set the shunt in a coupling state when an ESD event is sensed on one of the supply rails. The protection circuit further comprises a voltage booster arranged between the output of the trigger and the control terminal of the shunt to boost the shunt control voltage.
摘要翻译：静电放电保护电路耦合到集成电路的电源轨和接地电源轨，并且包括配置成耦合供电轨的至少一个分流器和被配置为在输出上向控制端施加分流控制电压的触发器的分流器，以在一个电源轨上感测到ESD事件时将分流器设置在耦合状态。保护电路还包括设置在触发器的输出端和分流器的控制端之间的升压器以升压分路控制电压的升压器。

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