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31. 发明申请

US20150364613A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150364613A1
公开(公告)日：2015-12-17
申请号：US14821571
申请日：2015-08-07
申请人： FUJI ELECTRIC CO., LTD.
发明人： Yuichi ONOZAWA , Takashi YOSHIMURA , Hiroshi TAKISHITA
IPC分类号： H01L29/872 , H01L29/66 , H01L21/268 , H01L21/225 , H01L21/304 , H01L21/324 , H01L29/06 , H01L21/263
CPC分类号： H01L29/872 , H01L21/221 , H01L21/225 , H01L21/2253 , H01L21/263 , H01L21/2636 , H01L21/26506 , H01L21/268 , H01L21/304 , H01L21/324 , H01L29/0619 , H01L29/0623 , H01L29/0626 , H01L29/32 , H01L29/36 , H01L29/66143 , H01L29/7395 , H01L29/8611
摘要： Provided is a semiconductor device and a method for forming the same. The device has a substrate including one and another surfaces. A first semiconductor region of a first conductivity type is formed in the substrate. A second conductivity type, second semiconductor region is provided in a first surface layer, that includes the one surface, of the substrate. A first electrode is in contact with the second semiconductor region to form a junction therebetween. A first conductivity type, third semiconductor region is provided in a second surface layer, that includes the another surface, of the substrate. The third semiconductor region has a higher impurity concentration than the first semiconductor region. A fourth semiconductor region of the second conductivity type is provided in the first semiconductor region at a location deeper than the third semiconductor region from the another surface. A second electrode is in contact with the third semiconductor region.
摘要翻译：提供一种半导体器件及其形成方法。该装置具有包括一个和另一个表面的基板。在衬底中形成第一导电类型的第一半导体区域。第二导电类型的第二半导体区域设置在包括基板的一个表面的第一表面层中。第一电极与第二半导体区域接触以在它们之间形成接合。第一导电类型的第三半导体区域设置在包括基板的另一表面的第二表面层中。第三半导体区域的杂质浓度比第一半导体区域高。第二导电类型的第四半导体区域从第二半导体区域设置在比另一表面更靠近第三半导体区域的位置。第二电极与第三半导体区域接触。

32. 发明授权

US09190418B2 Junction butting in SOI transistor with embedded source/drain 有权
标题翻译：具有嵌入式源极/漏极的SOI晶体管中的结对接
公开(公告)号：US09190418B2
公开(公告)日：2015-11-17
申请号：US14217572
申请日：2014-03-18
申请人： International Business Machines Corporation
发明人： Anthony I. Chou , Murshed M. Chowdhury , Arvind Kumar , Robert R. Robison
IPC分类号： H01L21/76 , H01L27/12 , H01L29/66 , H01L21/84 , H01L21/324 , H01L21/225 , H01L21/265 , H01L29/167
CPC分类号： H01L27/1203 , H01L21/225 , H01L21/265 , H01L21/324 , H01L21/84 , H01L29/165 , H01L29/167 , H01L29/6653 , H01L29/6656 , H01L29/66636
摘要： After forming source/drain trenches within a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, portions of the trenches adjacent channel regions of a semiconductor structure are covered either by sacrificial spacers formed on sidewalls of the trenches or by photoresist layer portions. The sacrificial spacers or photoresist layer portions shield portions of the top semiconductor layer underneath the trenches from subsequent ion implantation for forming junction butting. The ion implantation regions thus are confined only in un-shielded, sublayered portions of the top semiconductor layer that are away from the channel regions of the semiconductor structure. The width of the ion implantation regions are controlled such that the implanted dopants do not diffuse into the channel regions during subsequent thermal cycles so as to suppress the short channel effects.
摘要翻译：在绝缘体上半导体（SOI）衬底的顶部半导体层中形成源极/漏极沟槽之后，半导体结构的相邻沟道区的沟槽的部分被形成在沟槽的侧壁上的牺牲隔离物或由光刻胶层部分。牺牲间隔物或光致抗蚀剂层部分屏蔽沟槽下方的顶部半导体层的部分以及后续的离子注入以形成结对接。因此，离子注入区仅限于远离半导体结构的沟道区的顶部半导体层的未屏蔽的亚层部分。控制离子注入区域的宽度，使得注入的掺杂剂在随后的热循环期间不扩散到沟道区域中，以便抑制短沟道效应。

33. 发明申请

US20150325440A1 Method for Forming a Semiconductor Device and Semiconductor Device 有权
标题翻译：用于形成半导体器件和半导体器件的方法
公开(公告)号：US20150325440A1
公开(公告)日：2015-11-12
申请号：US14706435
申请日：2015-05-07
申请人： Infineon Technologies AG
发明人： Hans-Joachim Schulze , Johannes Laven
IPC分类号： H01L21/02 , H01L29/36 , H01L27/04 , H01L21/266 , H01L21/225
CPC分类号： H01L21/26506 , H01L21/02378 , H01L21/02381 , H01L21/02389 , H01L21/02395 , H01L21/02529 , H01L21/02532 , H01L21/0254 , H01L21/02546 , H01L21/02658 , H01L21/02664 , H01L21/225 , H01L21/266 , H01L27/04 , H01L29/36 , H01L29/66348 , H01L29/7397 , H01L29/861
摘要： A method for forming a semiconductor device includes depositing an epitaxial layer on a semiconductor substrate, forming an oxygen diffusion region within the epitaxial layer by oxygen diffusion from the semiconductor substrate into a part of the epitaxial layer and tempering at least the oxygen diffusion region of the epitaxial layer at a temperature between 400° C. and 480° C. for more than 15 minutes.
摘要翻译：一种形成半导体器件的方法包括：在半导体衬底上沉积外延层，通过从半导体衬底向半导体衬底扩散到外延层的一部分中，在外延层中形成氧扩散区，并至少回火外延层在400℃和480℃之间的温度下超过15分钟。

34. 发明授权

US09184277B2 Super junction semiconductor device comprising a cell area and an edge area 有权
标题翻译：超结半导体器件包括单元区域和边缘区域
公开(公告)号：US09184277B2
公开(公告)日：2015-11-10
申请号：US13664924
申请日：2012-10-31
申请人： Infineon Technologies Austria AG
发明人： Armin Willmeroth , Franz Hirler , Hans Weber , Markus Schmitt , Thomas Wahls , Rolf Weis
IPC分类号： H01L29/78 , H01L21/265
CPC分类号： H01L29/0634 , H01L21/225 , H01L21/265 , H01L21/26506 , H01L21/266 , H01L21/324 , H01L29/0696 , H01L29/66712 , H01L29/7802 , H01L29/7811
摘要： A super junction semiconductor device may include one or more doped zones in a cell area. A drift layer is provided between a doped layer of a first conductivity type and the one or more doped zones. The drift layer includes first regions of the first conductivity type and second regions of a second conductivity type, which is the opposite of the first conductivity type. In an edge area that surrounds the cell area, the first regions may include first portions separating the second regions in a first direction and second portions separating the second regions in a second direction orthogonal to the first direction. The first and second portions are arranged such that a longest second region in the edge area is at most half as long as a dimension of the edge area parallel to the longest second region.
摘要翻译：超结半导体器件可以在单元区域中包括一个或多个掺杂区域。在第一导电类型的掺杂层和一个或多个掺杂区之间提供漂移层。漂移层包括第一导电类型的第一区域和与第一导电类型相反的第二导电类型的第二区域。在围绕单元区域的边缘区域中，第一区域可以包括在第一方向上分离第二区域的第一部分和在与第一方向正交的第二方向上分离第二区域的第二部分。第一和第二部分被布置成使得边缘区域中最长的第二区域是与最长的第二区域平行的边缘区域的尺寸的至多一半的一半。

35. 发明申请

US20150318384A1 Bipolar Transistor 有权
标题翻译：双极晶体管
公开(公告)号：US20150318384A1
公开(公告)日：2015-11-05
申请号：US14267651
申请日：2014-05-01
申请人： Infineon Technologies AG
发明人： Josef Boeck , Wolfgang Liebl
IPC分类号： H01L29/732 , H01L21/324 , H01L29/06 , H01L21/225 , H01L29/66 , H01L29/417
CPC分类号： H01L29/732 , H01L21/225 , H01L21/324 , H01L29/0649 , H01L29/0804 , H01L29/1004 , H01L29/41708 , H01L29/66234 , H01L29/66272 , H01L29/7371
摘要： A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers.
摘要翻译：公开了双极晶体管和制造双极晶体管的方法。在一个实施例中，双极晶体管包括半导体本体，其包括集电极区域和布置在集电极区域顶部的基极区域，该集电极区域掺杂有第二掺杂类型的掺杂剂，并且该基极区域至少部分掺杂有掺杂剂第一掺杂类型和布置在基极区域顶部的绝缘间隔物。所述半导体本体还包括半导体层，所述半导体层包括布置在所述基极区域上并由所述间隔物横向包围的发射极区域，所述发射极区域掺杂有与所述基极区域形成pn结的所述第二掺杂类型的掺杂剂，其中所述发射极区域通过间隔件的底侧完全位于水平面之上。

36. 发明申请

US20150311303A1 STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS 审中-公开
公开(公告)号：US20150311303A1
公开(公告)日：2015-10-29
申请号：US14739686
申请日：2015-06-15
申请人： International Business Machines Corporation
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L29/423 , H01L21/8234 , H01L21/28 , H01L29/40 , H01L21/225
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

37. 发明申请

US20150287650A1 III-V, GE, OR SIGE FIN BASE LATERAL BIPOLAR TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译： III-V，GE或SIGM FIN基底横向双极晶体管结构和方法
公开(公告)号：US20150287650A1
公开(公告)日：2015-10-08
申请号：US14245683
申请日：2014-04-04
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Gen P. Lauer , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L21/84 , H01L21/02 , H01L21/24 , H01L27/12 , H01L21/225 , H01L29/66 , H01L29/735 , H01L21/3065 , H01L21/324
CPC分类号： H01L21/845 , H01L21/02532 , H01L21/02538 , H01L21/0257 , H01L21/02595 , H01L21/225 , H01L21/2254 , H01L21/2255 , H01L21/244 , H01L21/3065 , H01L21/324 , H01L21/8249 , H01L27/0623 , H01L27/0886 , H01L27/0924 , H01L27/10826 , H01L27/10879 , H01L27/1211 , H01L29/06 , H01L29/0673 , H01L29/1008 , H01L29/165 , H01L29/41791 , H01L29/42392 , H01L29/6625 , H01L29/6631 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66772 , H01L29/66795 , H01L29/6681 , H01L29/735 , H01L29/775 , H01L29/7831 , H01L29/785 , H01L29/78696
摘要： In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. Fin hardmasks are formed on the wafer. A dummy gate is formed on the wafer, over the fin hardmasks. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer and the dummy gate is removed selective to the dielectric filler layer so as to form a trench in the filler layer. Fins are patterned in the wafer using the fin hardmasks exposed within the trench, wherein the fins will serve as a base region of the bipolar transistor device. The fins are recessed in the base region. The base region is re-grown from an epitaxial SiGe, Ge or III-V semiconductor material. A contact is formed to the base region.
摘要翻译：一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。翅片硬掩模形成在晶片上。在晶片上，在翅片硬掩模上形成虚拟栅极。晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。将介电填料层沉积在晶片上，并且将虚拟栅极选择性地去除介电填料层，以便在填料层中形成沟槽。使用暴露在沟槽内的散热片硬掩模，在晶片中图案化鳍片，其中鳍片将用作双极晶体管器件的基极区域。翅片凹入基部区域。从外延SiGe，Ge或III-V半导体材料再生长基极区。在基部区域形成接触。

38. 发明申请

US20150279937A1 STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS 审中-公开
公开(公告)号：US20150279937A1
公开(公告)日：2015-10-01
申请号：US14739669
申请日：2015-06-15
申请人： International Business Machines Corporation
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L29/10 , H01L21/477 , H01L21/324 , H01L29/51 , H01L29/49
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

39. 发明申请

US20150140773A1 METHODS OF FORMING INSULATIVE ELEMENTS 审中-公开
标题翻译：形成绝缘元素的方法
公开(公告)号：US20150140773A1
公开(公告)日：2015-05-21
申请号：US14596037
申请日：2015-01-13
申请人： Micron Technology, Inc.
发明人： Vassil Antonov , Jennifer K. Sigman , Vishwanath Bhat , Matthew N. Rocklein , Bhaskar Srinivasan , Chris Carlson
IPC分类号： H01L49/02 , H01L21/225 , H01L21/02
CPC分类号： H01L28/40 , H01G4/1209 , H01G4/1218 , H01G4/1236 , H01G4/1254 , H01G4/1272 , H01G4/306 , H01G4/33 , H01L21/02172 , H01L21/02356 , H01L21/225 , Y10T428/2495
摘要： Methods of forming an insulative element are described, including forming a first metal oxide material having a first dielectric constant, forming a second metal oxide material having a second dielectric constant different from the first, and heating at least portions of the structure to crystallize at least a portion of at least one of the first dielectric material and the second dielectric material. Methods of forming a capacitor are described, including forming a first electrode, forming a dielectric material with a first oxide and a second oxide over the first electrode, and forming a second electrode over the dielectric material. Structures including dielectric materials are also described.
摘要翻译：描述了形成绝缘元件的方法，包括形成具有第一介电常数的第一金属氧化物材料，形成具有与第一介电常数不同的第二介电常数的第二金属氧化物材料，并加热该结构的至少部分至少结晶第一电介质材料和第二电介质材料中的至少一个的一部分。描述了形成电容器的方法，包括形成第一电极，在第一电极上形成具有第一氧化物和第二氧化物的介电材料，以及在电介质材料上形成第二电极。还描述了包括电介质材料的结构。

40. 发明申请

US20150118833A1 METHOD OF MAKING SOURCE/DRAIN CONTACTS BY SPUTTERING A DOPED TARGET 审中-公开
标题翻译：通过喷射目标来制造源/排泄物接触的方法
公开(公告)号：US20150118833A1
公开(公告)日：2015-04-30
申请号：US14062741
申请日：2013-10-24
申请人： Applied Materials, Inc.
发明人： Jianxin LEI , Jothilingam RAMALINGAM , Chi-Nung NI
IPC分类号： H01L21/285 , H01L29/66 , C23C14/34 , H01L21/225
CPC分类号： H01L21/28506 , C23C14/16 , C23C14/3414 , C23C14/5813 , H01L21/225 , H01L21/2254 , H01L21/28518 , H01L21/2855 , H01L21/76843 , H01L21/76855 , H01L29/456 , H01L29/66477
摘要： A method of depositing a contact layer material includes sputtering a target including a metal and a dopant. The contact layer material is conductive and may be used in a transistor device to connect a conductive region, such as a source region or a drain region of metal-oxide semiconductor field effect transistor, to a contact plug. The contact plug is used to connect the source/drain region formed in a semiconducting substrate to metal wiring layers formed above the gate level of a semiconductor device. The resulting contact layer may be a metal silicide including the dopant. In some embodiments, the sputtered metal may be nickel and the dopant may be phosphorous and the resulting contact layer a nickel silicide doped with phosphorous. Embodiments described, in general, can provide reduced contact resistance and thus improved performance in semiconductor devices.
摘要翻译：沉积接触层材料的方法包括溅射包括金属和掺杂剂的靶。接触层材料是导电的，并且可以用在晶体管器件中以将诸如金属氧化物半导体场效应晶体管的源极区域或漏极区域的导电区域连接到接触插塞。接触插头用于将形成在半导体衬底中的源极/漏极区域连接到形成在半导体器件的栅极级上方的金属布线层。所得到的接触层可以是包括掺杂剂的金属硅化物。在一些实施例中，溅射金属可以是镍，并且掺杂剂可以是磷，并且所得到的接触层是掺杂有磷的硅化镍。通常描述的实施例可以提供降低的接触电阻并因此提高半导体器件的性能。

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