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31. 发明申请

US20160268440A1 THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE 审中-公开
标题翻译：薄膜晶体管及其制造方法，阵列基板和显示器件
公开(公告)号：US20160268440A1
公开(公告)日：2016-09-15
申请号：US14408493
申请日：2014-05-29
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Xiang LIU
IPC分类号： H01L29/786 , H01L27/12 , H01L29/66
CPC分类号： H01L29/78606 , H01L27/1225 , H01L27/1262 , H01L29/42384 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L2029/42388
摘要： The disclosure discloses a thin film transistor and a fabrication method thereof, an array substrate and a display device. The thin film transistor comprises an active layer and an insulating layer adjacent to the active layer. The insulating layer comprises a first insulating layer, the first insulating layer comprises a first silicon oxide film and a second silicon oxide film, and the second silicon oxide film is in direct contact with the active layer. A density of the second silicon oxide film is larger than that of the first silicon oxide film.
摘要翻译：本公开公开了一种薄膜晶体管及其制造方法，阵列基板和显示装置。薄膜晶体管包括有源层和与有源层相邻的绝缘层。绝缘层包括第一绝缘层，第一绝缘层包括第一氧化硅膜和第二氧化硅膜，并且第二氧化硅膜与有源层直接接触。第二氧化硅膜的密度大于第一氧化硅膜的密度。

32. 发明授权

US09437503B1 Vertical FETs with variable bottom spacer recess 有权
标题翻译：具有可变底部间隔凹槽的垂直FET
公开(公告)号：US09437503B1
公开(公告)日：2016-09-06
申请号：US14978197
申请日：2015-12-22
申请人： International Business Machines Corporation
发明人： Hari V. Mallela , Reinaldo A. Vega , Rajasekhar Venigalla
IPC分类号： H01L21/20 , H01L21/8238 , H01L27/092 , H01L21/02 , H01L21/32
CPC分类号： H01L21/82385 , H01L21/02263 , H01L21/26566 , H01L21/32 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823864 , H01L21/823885 , H01L27/092 , H01L27/0922 , H01L29/0653 , H01L29/42392 , H01L29/4966 , H01L29/78618 , H01L29/78642 , H01L29/78696 , H01L2029/42388
摘要： A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a second source/drain of a second transistor on the substrate adjacent to the first source/drain, an isolation region arranged in the substrate between the first source/drain and the second source/drain; depositing a spacer material on the first source/drain; depositing the spacer material on the second source/drain; forming a first channel extending from the first source drain and through the spacer material; forming a second channel extending from the second source/drain and through the spacer material; wherein the spacer material on the first source/drain forms a first spacer and the spacer material on the second source/drain forms a second spacer, the first spacer being different in thickness than the second spacer.
摘要翻译：在垂直晶体管器件中形成可变间隔物的方法包括在衬底上形成第一晶体管的第一源极/漏极; 在与第一源极/漏极相邻的衬底上形成第二晶体管的第二源极/漏极;布置在第一源极/漏极和第二源极/漏极之间的衬底中的隔离区域; 在第一源极/漏极上沉积间隔物; 将间隔物材料沉积在第二源极/漏极上; 形成从所述第一源极延伸并穿过所述间隔物材料的第一通道; 形成从所述第二源极/漏极延伸并穿过所述间隔物材料的第二通道; 其中所述第一源极/漏极上的间隔物材料形成第一间隔物，并且所述第二源极/漏极上的间隔物材料形成第二间隔物，所述第一间隔物的厚度与所述第二间隔物的厚度不同。

33. 发明申请

US20160225873A1 TRENCHED GATE WITH SIDEWALL AIRGAP SPACER 有权
标题翻译：带有侧壁空气隔离器的高空门
公开(公告)号：US20160225873A1
公开(公告)日：2016-08-04
申请号：US14613667
申请日：2015-02-04
申请人： International Business Machines Corporation
发明人： Effendi Leobandung
IPC分类号： H01L29/51 , H01L29/66 , H01L29/786
CPC分类号： H01L29/66742 , H01L29/42384 , H01L29/4908 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/66621 , H01L29/66772 , H01L29/66969 , H01L29/786 , H01L29/78636 , H01L29/78654 , H01L29/78681 , H01L29/78684 , H01L2029/42388
摘要： A method for fabricating a semiconductor device may include receiving a device substrate comprising a channel layer and a source or drain layer, forming a gate trench within the source or drain layer of the device substrate, depositing a gate dielectric layer and one or more additional gate layers onto the bottom and sidewalls of the gate trench, and removing a substantial portion of at least the gate dielectric layer from the sidewalls of the gate trench to form a left and a right sidewall airgap adjacent to the sidewalls of the gate trench. A corresponding semiconductor device may include a device substrate comprising a channel layer and a source or drain layer, a gate trench formed within the source or drain layer of the device substrate and a sidewall airgap formed adjacent to the sidewalls of the gate trench.
摘要翻译：一种用于制造半导体器件的方法可以包括接收包括沟道层和源极或漏极层的器件衬底，在器件衬底的源极或漏极层内形成栅极沟槽，沉积栅极电介质层和一个或多个附加栅极层到栅极沟槽的底部和侧壁上，以及从栅极沟槽的侧壁去除至少栅极电介质层的大部分，以形成邻近栅极沟槽的侧壁的左侧壁和右侧壁气隙。相应的半导体器件可以包括器件衬底，其包括沟道层和源极或漏极层，形成在器件衬底的源极或漏极层内的栅极沟槽和邻近栅极沟槽的侧壁形成的侧壁气隙。

34. 发明申请

US20160172500A1 Semiconductor Device and Method for Manufacturing the Same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20160172500A1
公开(公告)日：2016-06-16
申请号：US14963945
申请日：2015-12-09
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki , Tetsuhiro TANAKA , Akihisa SHIMOMURA , Yasumasa YAMANE , Ryo TOKUMARU , Yuhei SATO , Kazuhiro TSUTSUI
IPC分类号： H01L29/786 , H01L21/02 , H01L29/423 , H01L29/66 , H01L29/49 , H01L29/51
CPC分类号： H01L29/7869 , C23C14/08 , C23C14/3414 , H01L21/02266 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1207 , H01L27/1225 , H01L29/42384 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/66969 , H01L29/78648 , H01L29/78696 , H01L2029/42388
摘要： A transistor with stable electrical characteristics is provided. The transistor includes a first insulator over a substrate; first to third oxide insulators over the first insulator; a second insulator over the third oxide insulator; a first conductor over the second insulator; and a third insulator over the first conductor. An energy level of a conduction band minimum of each of the first and second oxide insulators is closer to a vacuum level than that of the oxide semiconductor is. An energy level of a conduction band minimum of the third oxide insulator is closer to the vacuum level than that of the second oxide insulator is. The first insulator contains oxygen. The number of oxygen molecules released from the first insulator measured by thermal desorption spectroscopy is greater than or equal to 1E14 molecules/cm2 and less than or equal to 1E16 molecules/cm2.
摘要翻译：提供具有稳定电特性的晶体管。晶体管包括在衬底上的第一绝缘体; 第一绝缘子上的第一至第三绝缘体; 在所述第三氧化物绝缘体上的第二绝缘体; 第二绝缘体上的第一导体; 以及在第一导体上的第三绝缘体。每个第一和第二氧化物绝缘体的导带最小值的能级比氧化物半导体的能级更接近真空度。第三氧化物绝缘体的导带最小值的能级比第二氧化物绝缘体的能级更接近真空度。第一绝缘体包含氧。通过热解吸光谱测定从第一绝缘体释放的氧分子的数量大于或等于1E14分子/ cm 2且小于或等于1E16分子/ cm 2。

35. 发明授权

US09337210B2 Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors 有权
标题翻译：垂直铁电场效应晶体管结构，包括一对垂直铁电场效应晶体管的结构，铁电场效应晶体管的垂直串和横向相对的垂直铁电场效应晶体管的垂直串
公开(公告)号：US09337210B2
公开(公告)日：2016-05-10
申请号：US13964309
申请日：2013-08-12
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , Chandra Mouli , Gurtej S. Sandhu
IPC分类号： H01L27/115 , H01L21/02 , H01L21/28 , H01L29/51 , H01L29/66 , G11C11/22
CPC分类号： H01L27/11597 , G11C11/22 , H01L21/02568 , H01L21/28291 , H01L27/11514 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L27/11585 , H01L27/1159 , H01L29/0649 , H01L29/1037 , H01L29/24 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/516 , H01L29/6684 , H01L29/7827 , H01L29/78642 , H01L29/78681 , H01L2029/42388
摘要： A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.
摘要翻译：垂直铁电场效应晶体管结构包括隔离芯。过渡金属二硫属元素材料环绕隔离芯并具有1个单层至7个单层的侧壁厚度。铁电栅极电介质材料围绕过渡金属二硫属元素材料。导电栅极材料围绕铁电栅极电介质材料。过渡金属二硫属元素材料在导电栅极材料的高度向内和向外向外延伸。导电接触件直接抵靠过渡金属二硫属化物材料的侧向外侧壁，其是导电栅极材料的顶部向内，或b）导电栅极材料的向外侧。公开了其他实施例。

36. 发明授权

US09312146B2 Manufacturing method of a thin film transistor 有权
标题翻译：薄膜晶体管的制造方法
公开(公告)号：US09312146B2
公开(公告)日：2016-04-12
申请号：US14354320
申请日：2013-10-29
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Xiangyong Kong , Jun Cheng , Dongfang Wang , Guangcai Yuan
IPC分类号： H01L21/8234 , H01L21/445 , H01L29/417 , H01L29/786 , H01L29/66 , H01L29/423 , H01L27/12
CPC分类号： H01L21/445 , H01L27/1288 , H01L29/41733 , H01L29/41758 , H01L29/41775 , H01L29/42384 , H01L29/66969 , H01L29/78618 , H01L29/78621 , H01L29/7869 , H01L2029/42388
摘要： Embodiments of the invention provide a thin film transistor and a manufacturing method thereof and a display device. The thin film transistor includes a gate electrode, a gate insulation layer, an active layer, an ohmic contact layer, a source electrode and a drain electrode, and the source electrode and the drain electrode are connected to the active layer by the ohmic contact layer. The ohmic contact layer is provided at a lateral side of the active layer and contacts the lateral side of the active layer.
摘要翻译：本发明的实施例提供一种薄膜晶体管及其制造方法和显示装置。薄膜晶体管包括栅电极，栅极绝缘层，有源层，欧姆接触层，源电极和漏电极，源电极和漏电极通过欧姆接触层连接到有源层。欧姆接触层设置在有源层的侧面并接触有源层的侧面。

37. 发明授权

US09093543B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09093543B2
公开(公告)日：2015-07-28
申请号：US14521540
申请日：2014-10-23
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Masashi Tsubuku
IPC分类号： H01L29/04 , H01L29/786 , H01L29/10 , H01L29/423
CPC分类号： H01L29/7869 , H01L29/1033 , H01L29/42384 , H01L29/78693 , H01L2029/42388
摘要： To improve switching characteristics of a transistor in which a channel is formed in an oxide semiconductor layer. A parasitic channel is formed at an end portion of the oxide semiconductor layer because a source and a drain of the transistor are electrically connected to the end portion. That is, when at least one of the source and the drain of the transistor is not electrically connected to the end portion, the parasitic channel is not formed at the end portion. In view of this, a transistor having a structure in which at least one of a source and a drain of the transistor is not or less likely to be electrically connected to an end portion of an oxide semiconductor layer is provided.
摘要翻译：为了改善在氧化物半导体层中形成沟道的晶体管的开关特性。由于晶体管的源极和漏极电连接到端部，所以在氧化物半导体层的端部形成寄生沟道。也就是说，当晶体管的源极和漏极中的至少一个没有电连接到端部时，在端部处不形成寄生沟道。鉴于此，提供一种晶体管，其晶体管的源极和漏极中的至少一个不或多或少可能电连接到氧化物半导体层的端部。

38. 发明申请

US20150179460A1 LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译：低温聚硅薄膜晶体管及其制造方法
公开(公告)号：US20150179460A1
公开(公告)日：2015-06-25
申请号：US14241764
申请日：2014-01-23
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Xiangyang Xu
IPC分类号： H01L21/28 , H01L29/786 , H01L29/51 , H01L29/66
CPC分类号： H01L21/28229 , H01L21/28158 , H01L29/42384 , H01L29/4908 , H01L29/513 , H01L29/66757 , H01L29/78675 , H01L2029/42388
摘要： The present disclosure relates to a low temperature poly-silicon thin film transistor which possesses electrical characteristics and reliability, and a method of manufacturing the thin film transistor. The low temperature poly-silicon thin film transistor at least includes a gate insulating layer which is a composite insulating layer comprising at least three dielectric layers, wherein the compactness of each dielectric layer successively increases in order of the formation sequence thereof in the manufacturing process. Because the relation between the compactness of each layer of the composite insulating layer and that of the others thereof is taken into account according to the present disclosure, each layer in the composite insulating layer of the low temperature poly-silicon thin film transistor manufactured by the method according to the present disclosure can have enhanced surface contact characteristic and thin film continuity. The thickness of each layer in the composite insulating layer is further considered, so that the parasitic capacitance can be effectively reduced, and thus the response rate of the transistor can be improved. Namely, by improving the GI film forming quality, the electrical characteristic and reliability of the low temperature poly-silicon thin film transistor can be improved
摘要翻译：本公开涉及具有电特性和可靠性的低温多晶硅薄膜晶体管，以及制造薄膜晶体管的方法。低温多晶硅薄膜晶体管至少包括栅极绝缘层，其是包括至少三个电介质层的复合绝缘层，其中每个电介质层的致密度在制造过程中依次形成顺序。由于根据本公开考虑了复合绝缘层的各层的紧密度与其他层的紧密度之间的关系，所以由低温多晶硅薄膜晶体管制造的复合绝缘层中的每个层根据本公开的方法可以具有增强的表面接触特性和薄膜连续性。进一步考虑复合绝缘层中的各层的厚度，从而能够有效地降低寄生电容，从而能够提高晶体管的响应率。也就是说，通过提高GI成膜质量，可以提高低温多晶硅薄膜晶体管的电特性和可靠性

39. 发明授权

US09064967B2 Semiconductor element, semiconductor device, and method for manufacturing the same 有权
标题翻译：半导体元件，半导体器件及其制造方法
公开(公告)号：US09064967B2
公开(公告)日：2015-06-23
申请号：US14472602
申请日：2014-08-29
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hideomi Suzawa , Motomu Kurata , Mayumi Mikami
IPC分类号： H01L29/788 , H01L21/336 , H01L29/786 , H01L27/12 , H01L29/417 , H01L27/108 , H01L29/12 , H01L29/66
CPC分类号： H01L29/7869 , H01L27/108 , H01L27/1225 , H01L29/12 , H01L29/41733 , H01L29/42384 , H01L29/66969 , H01L29/78648 , H01L29/78696 , H01L2029/42388
摘要： The semiconductor element includes an oxide semiconductor layer on an insulating surface; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer. The source electrode layer and the drain electrode layer have sidewalls which are in contact with a top surface of the oxide semiconductor layer.
摘要翻译：半导体元件在绝缘表面上包括氧化物半导体层; 氧化物半导体层上的源电极层和漏电极层; 氧化物半导体层上的栅极绝缘层，源极电极层和漏极电极层; 以及栅极绝缘层上的栅极电极层。源电极层和漏电极层具有与氧化物半导体层的顶表面接触的侧壁。

40. 发明申请

US20150108472A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150108472A1
公开(公告)日：2015-04-23
申请号：US14518259
申请日：2014-10-20
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Hideomi Suzawa , Tetsuhiro Tanaka , Yuhei Sato , Sachiaki Tezuka , Shunpei Yamazaki
IPC分类号： H01L29/786 , H01L29/51
CPC分类号： H01L29/78648 , H01L27/1225 , H01L27/1255 , H01L29/41733 , H01L29/41766 , H01L29/42368 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L29/78693 , H01L29/78696 , H01L2029/42388
摘要： A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween.
摘要翻译：提供具有高场效应迁移率的晶体管。提供具有稳定电特性的晶体管。提供了处于断开状态（非导通状态）的小电流的晶体管。提供了包括这种晶体管的半导体器件。第一电极形成在衬底上，第一绝缘层与第一电极的侧表面相邻地形成，并且形成第二绝缘层以覆盖第一绝缘层并与第一绝缘层的至少一部分表面接触第一个电极。第一电极的表面由不容易透过杂质元素的导电材料形成。第二绝缘层由不容易透过杂质元素的绝缘材料形成。在第一电极上形成氧化物半导体层，其间设置有第三绝缘层。

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