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31. 发明申请

US20160042775A1 SEMICONDUCTOR MEMORY DEVICE FOR CONDUCTING MONITORING OPERATION TO VERIFY READ AND WRITE OPERATIONS 审中-公开
标题翻译：用于进行监视操作的半导体存储器件，以验证读取和写入操作
公开(公告)号：US20160042775A1
公开(公告)日：2016-02-11
申请号：US14887257
申请日：2015-10-19
申请人： SK hynix Inc.
发明人： Jin Ah KIM
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/1084 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/4096
摘要： A semiconductor memory device includes, in part, a first data I/O block and a second data I/O block. During a write operation, the first data I/O block transmits input data supplied through a first pad to a first global I/O line, and further generates a write internal signal. The second data I/O block transmits the write internal signal to a second pad in response to a monitor enable signal. During a read operation, the first data I/O block supplies data from the first global I/O line to a first pad, and further generates a read internal signal. The second data I/O block transmits the read internal signal to the second pad in response to a monitor enable signal.
摘要翻译：半导体存储器件部分地包括第一数据I / O块和第二数据I / O块。在写入操作期间，第一数据I / O块将通过第一焊盘提供的输入数据发送到第一全局I / O线，并进一步产生写入内部信号。响应于监视使能信号，第二数据I / O块将写内部信号发送到第二焊盘。在读操作期间，第一数据I / O块将数据从第一全局I / O线提供给第一焊盘，并进一步产生读内部信号。第二数据I / O块响应于监视使能信号将读取的内部信号发送到第二焊盘。

32. 发明授权

US09213553B2 System and method for configuring drivers 有权
标题翻译：用于配置驱动程序的系统和方法
公开(公告)号：US09213553B2
公开(公告)日：2015-12-15
申请号：US14046738
申请日：2013-10-04
申请人： Micron Technology, Inc.
发明人： Sujeet Ayyapureddi , Raghukiran Sreeramaneni , Suryanarayana B. Tatapudi
IPC分类号： H03K17/16 , G06F9/44 , G11C7/04 , G11C7/10
CPC分类号： G06F9/4411 , G11C7/04 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C2207/2254
摘要： Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.
摘要翻译：提供了驱动器系统和方法，例如包括识别驾驶员的过程角的那些; 并基于识别的过程角来配置驱动程序。另外的实施例提供了一种方法，其包括检测驾驶员的过程角，基于检测到的过程角度来设置校准电路的参考电压，以及基于参考电压配置驾驶员。

33. 发明授权

US09196319B2 Pre-charge voltage generation and power saving modes 有权
标题翻译：预充电电压和省电模式
公开(公告)号：US09196319B2
公开(公告)日：2015-11-24
申请号：US14216024
申请日：2014-03-17
申请人： Conversant Intellectual Property Management Inc.
发明人： Valerie Lines , HakJune Oh
IPC分类号： G11C5/14 , G11C7/10 , G11C8/08
CPC分类号： G11C5/148 , G11C5/147 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C2207/2227
摘要： A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.
摘要翻译：系统包括电压发生器，以产生用于对存储器电路中的一个或多个信号进行预充电的预充电电压信号。一个或多个信号可以是用于访问存储器的数据总线。电压发生器可以包括指示存储器电路是否被设置为省电模式的输入。根据一个实施例，输入调节由电压发生器产生的预充电电压信号的幅度。这种实施例对于常规方法是有用的，因为调节预充电电压可导致功率节省。例如，在省电模式下，电压发生器电路可以将预充电电压调整为减小与预充电电压相关联的漏电流量的值。减少相对于预充电电压的泄漏意味着所节省的功率可以用于其他有用的目的。

34. 发明申请

US20150318028A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20150318028A1
公开(公告)日：2015-11-05
申请号：US14800256
申请日：2015-07-15
申请人： Kyo-min SOHN
发明人： Kyo-min SOHN
IPC分类号： G11C7/10
CPC分类号： G11C7/1009 , G11C5/02 , G11C5/06 , G11C7/1006 , G11C7/1045 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/1675 , G11C11/4085 , G11C11/4096 , G11C11/4097 , G11C2211/5647
摘要： A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.
摘要翻译：半导体存储器件包括第一区域中的多个存储体，输入数据信号的数据端子，数据端子处于第二区域，反相电路使输入数据信号反相或不反相响应于指示输入数据信号是否已被反相的反相控制信号，其中为多个存储体中的每一个设置至少一个反相电路。

35. 发明授权

US09177650B2 Memory device with multiple cell write for a single input-output in a single write cycle 有权
标题翻译：在单个写入周期内具有多个单元写入单个输入输出的存储器件
公开(公告)号：US09177650B2
公开(公告)日：2015-11-03
申请号：US14035507
申请日：2013-09-24
申请人： Integrated Silicon Solution, Inc.
发明人： MingShiang Wang , Kyoung Chon Jin
IPC分类号： G11C16/08 , G11C16/20
CPC分类号： G11C16/08 , G11C7/1096 , G11C16/0483 , G11C16/20
摘要： A non-volatile memory device incorporates a write buffer within a multi-level column decoder to enable multiple memory cells associated with a single write driver to be written in parallel. In this manner, in a non-volatile memory such as a flash memory that performs batch write operation, a group of data bits for a single I/O can be written to the memory cells at a time, thereby reducing the number of write cycles required for writing a block of program data and increasing the speed of write operation.
摘要翻译：非易失性存储器装置在多级列解码器内并入写入缓冲器，以使得能够并行地写入与单个写入驱动器相关联的多个存储器单元。以这种方式，在执行批量写入操作的诸如闪存的非易失性存储器中，可以一次将一个单个I / O的一组数据位写入存储单元，从而减少写周期数写入程序数据块并增加写入操作的速度所需的。

36. 发明授权

US09064590B2 Driving method of semiconductor storage device and semiconductor storage device 有权
标题翻译：半导体存储器件和半导体存储器件的驱动方法
公开(公告)号：US09064590B2
公开(公告)日：2015-06-23
申请号：US13780791
申请日：2013-02-28
申请人： Kabushiki Kaisha Toshiba
发明人： Yoshihiro Ueda
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15 , G11C11/16 , G11C7/06 , G11C7/10
CPC分类号： G11C11/1673 , G11C7/065 , G11C7/1063 , G11C7/1096
摘要： In a memory, a signal holder holds voltages according to data in the storage elements. A busy-signal controller controls a busy-signal. The busy-signal determines whether to permit or reject reception of a read/write enable signal. During reception of the read/write enable signal is rejected, the signal holder holds a first to a third voltages. The first voltage corresponds to target data stored in a first storage element. The second voltage corresponds to first sample data of first logic written to the first storage element. The third voltage corresponds to second sample data of second logic. A sense amplifier detects logic of the target data by comparing a read signal of the first voltage with a reference signal generated by the second and third voltages. The write driver writes the target data/write data to the first storage element. After writing, the reception of the read/write enable signal is permitted.
摘要翻译：在存储器中，信号保持器根据存储元件中的数据保持电压。忙信号控制器控制忙信号。忙信号确定是允许还是拒绝接收读/写使能信号。在读/写使能信号的接收被拒绝时，信号保持器保持第一至第三电压。第一电压对应于存储在第一存储元件中的目标数据。第二电压对应于写入第一存储元件的第一逻辑的第一采样数据。第三电压对应于第二逻辑的第二取样数据。读出放大器通过将第一电压的读取信号与由第二和第三电压产生的参考信号进行比较来检测目标数据的逻辑。写驱动器将目标数据/写数据写入第一存储元件。写入后，允许读/写允许信号的接收。

37. 发明申请

US20150146470A1 WRITE ASSIST CIRCUIT FOR WRITE DISTURBED MEMORY CELL 有权
标题翻译：用于写入干扰记忆体的写入辅助电路
公开(公告)号：US20150146470A1
公开(公告)日：2015-05-28
申请号：US14089819
申请日：2013-11-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Atul KATOCH
IPC分类号： G11C7/24 , G11C5/06
CPC分类号： G11C7/24 , G11C5/063 , G11C7/1075 , G11C7/109 , G11C7/1096 , G11C7/22 , G11C8/16 , G11C11/412 , G11C11/418 , G11C11/419
摘要： A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit. The second memory cell has a third port and a fourth port. The third port is associated with a third write assist circuit. The fourth port is associated with a fourth write assist circuit. The disturb control circuit is configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed.
摘要翻译：电路包括第一存储单元，第二存储单元和干扰控制电路。第一存储单元具有第一端口和第二端口。第一端口与第一写入辅助电路相关联。第二端口与第二写辅助电路相关联。第二存储单元具有第三端口和第四端口。第三端口与第三写入辅助电路相关联。第四端口与第四写辅助电路相关联。所述干扰控制电路被配置为根据所述第一端口，所述第二端口，所述第二端口，所述第二端口，所述第二端口，所述第二端口，所述第二端口，所述第二端口，所述第二端口，第三端口或第四端口被确定为被写入干扰。

38. 发明申请

US20150117078A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150117078A1
公开(公告)日：2015-04-30
申请号：US14504045
申请日：2014-10-01
申请人： Hidekaza Egawa
发明人： Hidekaza Egawa
IPC分类号： G11C11/4091 , G11C5/02
CPC分类号： G11C11/4091 , G11C5/02 , G11C5/025 , G11C7/065 , G11C7/1069 , G11C7/1096 , G11C11/4096
摘要： A semiconductor device includes a plurality of main amplifiers provided between memory cell arrays. One of the main amplifiers is disposed closer to one of the memory cell arrays than to the other of memory cell arrays, and the other of the main amplifiers is disposed closer to the other of the memory cell arrays than to the one of the memory cell arrays. Additional apparatus are disclosed.
摘要翻译：半导体器件包括设置在存储单元阵列之间的多个主放大器。主放大器中的一个被放置得比存储单元阵列中的另一个更靠近存储单元阵列之一，并且另一个主放大器被设置成比存储单元中的一个更靠近存储单元阵列中的另一个阵列公开了附加装置。

39. 发明授权

US09007866B2 Retention optimized memory device using predictive data inversion 有权
公开(公告)号：US09007866B2
公开(公告)日：2015-04-14
申请号：US13868884
申请日：2013-04-23
申请人： Invensas Corporation
发明人： David Edward Fisch , William C. Plants , Kent Stalnaker
IPC分类号： G11C5/14 , G11C29/52 , G11C7/02 , G11C7/10 , G11C11/4096 , G11C7/06 , G11C11/4091
CPC分类号： G11C11/4091 , G11C7/00 , G11C7/02 , G11C7/062 , G11C7/065 , G11C7/1006 , G11C7/1069 , G11C7/1096 , G11C11/4087 , G11C11/4096 , G11C29/52
摘要： A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

40. 发明授权

US08971133B1 Memory device and method of operation of such a memory device 有权
标题翻译：这种存储器件的存储器件和操作方法
公开(公告)号：US08971133B1
公开(公告)日：2015-03-03
申请号：US14037413
申请日：2013-09-26
申请人： ARM Limited
发明人： Bo Zheng , Jungtae Kwon , Gus Yeung , Yew Keong Chong
IPC分类号： G11C7/10 , G11C7/22 , G11C7/12 , G06F17/50
CPC分类号： G11C7/12 , G11C7/1096
摘要： A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.
摘要翻译：具有连接到核心电压电平的存储器单元阵列的存储器件，以及用于执行写入操作以便将数据写入到多个寻址的存储器单元中的存取电路。在执行写入操作之前，至少与包含寻址的存储器单元的阵列中的每列相关联的位线被预充电到外围电压电平。然后，字线驱动器电路被配置为在与包含寻址的存储器单元的阵列的行相关联的字线上的核心电压电平处断言字线信号。写复用驱动器电路断言多路复用控制信号以写入多路复用电路，然后根据多路复用器控制信号将每个寻址的存储器单元的位线耦合到写入驱动器电路，该多路复用器控制信号标识哪个列包含寻址的存储器单元。

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