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31. 发明申请

US20060030963A1 Sorting a group of integrated circuit devices for those devices requiring special testing 失效
公开(公告)号：US20060030963A1
公开(公告)日：2006-02-09
申请号：US11240178
申请日：2005-09-29
申请人： Raymond Beffa
发明人： Raymond Beffa
IPC分类号： G06F19/00
CPC分类号： G01R31/2894 , G01R31/31718 , G01R31/319 , G06F11/006 , H01L21/67271 , H01L22/14 , H01L22/20 , H01L2223/5444
摘要： A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing includes storing fabrication deviation data, probe data, and test data in association with the fuse ID of each of the devices indicating each of the devices requires either enhanced reliability testing or standard testing. The fuse ID of each of the devices is then automatically read before, during, or after standard testing of the devices. The testing process requirement data stored in association with the fuse ID of each of the devices is then accessed, and the devices are sorted in accordance with the accessed data into those devices requiring enhanced reliability testing and those requiring standard testing.

32. 发明授权

US06895548B2 Semiconductor testing apparatus and method for optimizing a wait time until stabilization of semiconductor device output signal 失效
标题翻译：用于优化等待时间直到半导体器件输出信号稳定的半导体测试装置和方法
公开(公告)号：US06895548B2
公开(公告)日：2005-05-17
申请号：US10050160
申请日：2002-01-18
申请人： Masatsugu Kitada , Motoyuki Katayama , Akiyoshi Kuramoto , Tatsuhisa Nii
发明人： Masatsugu Kitada , Motoyuki Katayama , Akiyoshi Kuramoto , Tatsuhisa Nii
IPC分类号： G01R31/319 , H03M13/00 , G01R31/28
CPC分类号： G01R31/319
摘要： A semiconductor testing apparatus includes a test program memory for storing a test program, a measuring/deciding section for receiving the test program and supplying a test signal to the semiconductor device with a wait time set to a predetermined value and detecting an optimal value of a wait time, after an elapse of the wait time, based on a response signal outputted from the semiconductor device and effecting an OK/NG decision on the electrical characteristics of the semiconductor device based on a result of the measurement and, if the result of the decision is found to be “NG”, remeasuring the electrical characteristics of the semiconductor device under a newly set wait time and effecting such remeasurement on the electrical characteristics of the semiconductor device at each newly set wait time until the result of such decision becomes “OK”.
摘要翻译：半导体测试装置包括用于存储测试程序的测试程序存储器，用于接收测试程序并将测试信号提供给半导体器件的测量/确定部件，其等待时间设置为预定值，并且检测最佳值基于从半导体器件输出的响应信号，等待时间等待时间，并且基于测量结果对半导体器件的电特性进行OK / NG判定，如果结果为发现判定为“NG”，在新设置的等待时间内重新测量半导体器件的电气特性，并在每个新设置的等待时间对半导体器件的电气特性进行这种重新测量，直到这种判定结果变为“OK “。

33. 发明授权

US06892333B2 IC measuring device 失效
标题翻译： IC测量装置
公开(公告)号：US06892333B2
公开(公告)日：2005-05-10
申请号：US10033252
申请日：2001-12-26
申请人： Toshiyuki Ohtaki , Mitsuru Kondo
发明人： Toshiyuki Ohtaki , Mitsuru Kondo
IPC分类号： G01R31/28 , G01R31/319 , G11B20/20
CPC分类号： G01R31/319
摘要： An IC measuring device constituted by a first timing generator (TG21) for outputting a pair of judgment strobe pulses (S21); a first edge detector (E21) for detecting the states of a data strobe (DCK2) at two time points within one test cycle on the basis of the pair of judgment strobe pulses (S21); a second timing generator (TG22) for outputting a pair of judgment strobe pulses (S22); a second edge detector (E22) for detecting the states of data at two time points within one test cycle on the basis of the pair of judgment strobe pulses (S22); and a judgment section (J22) for determining acceptance/rejection of the timing of the data with reference to the data strobe on the basis of the states of the data and the states of the data strobe.
摘要翻译：一种IC测量装置，由用于输出一对判断选通脉冲的第一定时发生器（TG21）构成; 第一边缘检测器（E21），用于基于所述一对判断选通脉冲来检测在一个测试周期内的两个时间点的数据选通（DCK 2）的状态（S21）; 用于输出一对判断选通脉冲的第二定时发生器（TG22）（S22）; 第二边缘检测器（E22），用于基于所述一对判断选通脉冲来检测在一个测试周期内的两个时间点的数据状态（S22）; 以及用于基于数据的状态和数据选通状态来参考数据选通来确定数据的定时的接受/拒绝的判断部分（J22）。

34. 发明授权

US06873927B2 Control method of an automatic integrated circuit full testing system 有权
标题翻译：自动集成电路全面测试系统的控制方法
公开(公告)号：US06873927B2
公开(公告)日：2005-03-29
申请号：US10368096
申请日：2003-02-18
申请人： Ming-Ren Chi , Peng-Chia Kuo
发明人： Ming-Ren Chi , Peng-Chia Kuo
IPC分类号： G01R31/26 , G01R31/28 , G01R31/319 , G06F11/00 , G06F11/273 , G06K9/00 , G06T7/00 , H01L21/66 , G06F19/00
CPC分类号： G06F11/273 , G01R31/2893 , G01R31/319 , G06T7/0008 , G06T2207/30148
摘要： A control method for an automatic integrated circuit full testing system. A control device is utilized to control the testing process of the automatic integrated circuit full testing system. The steps for controlling the control device include driving an automatic transport device to fetch test integrated circuits from an integrated circuit supply rack to various testing computer stations. An automatic plug/unplug tool is driven so that each integrated circuit is plugged into the connector of a corresponding testing computer. All the testing computers are triggered to carry out respective preset testing programs. An image sensor is driven to monitor the an output image of the testing computers so that any abnormality in the integrated circuits can be determined. Thereafter, the automatic plug/unplug tool is driven to unload the tested integrated circuit from the testing computer. The automatic transport device is driven to transfer the tested integrated circuit to various integrated circuit bins of an integrated circuit binning device according to the testing results.
摘要翻译：一种自动集成电路全面测试系统的控制方法。控制装置用于控制自动集成电路全面测试系统的测试过程。用于控制控制装置的步骤包括驱动自动传送装置以从集成电路供应架取得测试集成电路到各种测试计算机站。驱动自动插头/拔出工具，使每个集成电路插入对应的测试计算机的连接器。触发所有测试计算机执行相应的预设测试程序。驱动图像传感器来监视测试计算机的输出图像，从而可以确定集成电路中的任何异常。此后，驱动自动插拔/拔出工具，将测试的集成电路从测试计算机卸载。根据测试结果，自动传送装置被驱动以将测试的集成电路传送到集成电路装箱装置的各种集成电路板。

35. 发明授权

US06788993B2 Sorting a group of integrated circuit devices for those devices requiring special testing 失效
标题翻译：对需要特殊测试的那些设备对一组集成电路设备进行排序
公开(公告)号：US06788993B2
公开(公告)日：2004-09-07
申请号：US10379257
申请日：2003-03-03
申请人： Raymond J. Beffa
发明人： Raymond J. Beffa
IPC分类号： G06F1900
CPC分类号： G01R31/2894 , G01R31/31718 , G01R31/319 , G06F11/006 , H01L21/67271 , H01L22/14 , H01L22/20 , H01L2223/5444
摘要： A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing includes storing fabrication deviation data, probe data, and test data in association with the fuse ID of each of the devices indicating each of the devices requires either enhanced reliability testing or standard testing. The fuse ID of each of the devices is then automatically read before, during, or after standard testing of the devices. The testing process requirement data stored in association with the fuse ID of each of the devices is then accessed, and the devices are sorted in accordance with the accessed data into those devices requiring enhanced reliability testing and those requiring standard testing.
摘要翻译：将具有熔丝识别（ID）的类型的集成电路（IC）装置分类到需要增强的可靠性测试的那些装置和需要进行标准测试的装置的方法包括存储制造偏差数据，探针数据和与熔丝ID相关联的测试数据指示每个设备的每个设备需要增强的可靠性测试或标准测试。然后在设备的标准测试之前，期间或之后自动读取每个设备的熔丝ID。然后访问与每个设备的熔丝ID相关联地存储的测试过程要求数据，并且根据所访问的数据将设备分类到需要增强的可靠性测试的设备和需要标准测试的那些设备中。

36. 发明授权

US06762611B2 Test configuration and test method for testing a plurality of integrated circuits in parallel 失效
标题翻译：用于同时测试多个集成电路的测试配置和测试方法
公开(公告)号：US06762611B2
公开(公告)日：2004-07-13
申请号：US10010504
申请日：2001-12-05
申请人： Michael Hübner , Gunnar Krause , Justus Kuhn , Jochen Müller , Peter Pöchmüller , Jürgen Weidenhöfer
发明人： Michael Hübner , Gunnar Krause , Justus Kuhn , Jochen Müller , Peter Pöchmüller , Jürgen Weidenhöfer
IPC分类号： G01R1073
CPC分类号： G01R31/319 , G01R31/318505 , G01R31/318511 , G01R31/31905 , G11C29/006 , G11C29/48
摘要： A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.
摘要翻译：用于同时测试位于晶片上的多个集成电路，特别是快速半导体存储器模块的测试配置。测试配置包括用于提升属于测试系统的电信号线的承载板，用于产生与要测试的电路上的接触区域的电连接的接触针，以及布置在承载板上的多个有源模块。有源模块分别被分配给要并联测试的电路之一，并且每一个都被插入测试系统和要测试的相关电路之间的信号路径中。在优选实施例中，有源模块基于与载板的平面成直角的方向至少部分地重叠布置。

37. 发明申请

US20040124863A1 Method and probe card configuration for testing a plurality of integrated circuits in parallel 失效
标题翻译：用于同时测试多个集成电路的方法和探针卡配置
公开(公告)号：US20040124863A1
公开(公告)日：2004-07-01
申请号：US10736356
申请日：2003-12-15
申请人： Infineon Technologies AG
发明人： Michael Hubner , Gunnar Krause , Justus Kuhn , Jochen Muller , Peter Pochmuller , Jurgen Weidenhofer
IPC分类号： G01R031/02
CPC分类号： G01R31/319 , G01R31/318505 , G01R31/318511 , G01R31/31905 , G11C29/006 , G11C29/48
摘要： A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.
摘要翻译：用于同时测试位于晶片上的多个集成电路，特别是快速半导体存储器模块的测试配置。测试配置包括用于提升属于测试系统的电信号线的承载板，用于产生与要测试的电路上的接触区域的电连接的接触针，以及布置在承载板上的多个有源模块。有源模块分别被分配给要并联测试的电路之一，并且每一个都被插入测试系统和要测试的相关电路之间的信号路径中。在优选实施例中，有源模块基于与载板的平面成直角的方向至少部分地重叠布置。

38. 发明授权

US06757634B2 Methods and structure for maintaining state information to resume automated test processing after reset 有权
标题翻译：复位后维护状态信息恢复自动化测试处理的方法和结构
公开(公告)号：US06757634B2
公开(公告)日：2004-06-29
申请号：US10166513
申请日：2002-06-10
申请人： John M. Lara
发明人： John M. Lara
IPC分类号： G01R3100
CPC分类号： G01R31/319 , G06F11/2635
摘要： Methods and associated structure for saving and restoration of state information regarding progress of an automated test procedure to permit resumption of the automated test procedure following reset or failure of the automated test system. An automated test system in accordance with the present invention preferably saves state information in a non-volatile storage medium, such as a disk file, indicative of the progress of the test procedure. When the test system environment in which the automated test system is operable is reset or restarted, intentionally or due to failure, the automated test system retrieves previously saved state information from the non-volatile storage medium to resume the automated test process in accordance with the saved state information.
摘要翻译：用于保存和恢复关于自动测试程序进展的状态信息的方法和相关结构，以允许在自动测试系统复位或故障之后恢复自动测试程序。根据本发明的自动测试系统优选地将状态信息保存在表示测试过程进展的诸如磁盘文件的非易失性存储介质中。当自动化测试系统可操作的测试系统环境被有意地或由于故障而复位或重新启动时，自动测试系统从非易失性存储介质中检索先前保存的状态信息，以恢复自动化测试过程，保存状态信息。

39. 发明申请

US20040111231A1 INTEGRATED CIRCUITS HAVING POST-SILICON ADJUSTMENT CONTROL 有权
标题翻译：具有后置硅调整控制的集成电路
公开(公告)号：US20040111231A1
公开(公告)日：2004-06-10
申请号：US10707450
申请日：2003-12-15
发明人： Yoshiyuki Ando
IPC分类号： G06F019/00 , G01R031/00 , G01R027/28
CPC分类号： G01R31/31707 , G01R31/319
摘要： An integrated circuit system has a reference data table for holding information that is used to control at least one circuit block in the system and also has a power supply circuit, a body bias control circuit, a clock delivery circuit, a temperature monitor circuit, and/or a configuration control circuit. The performance of the system is improved by obtaining system performance data by testing the system at different supply voltages, different body-bias voltages, different clock speeds, and/or different temperatures. Values based on the data are entered into the reference data table. The power supply circuit, the body bias control circuit, the clock delivery circuit, and/or the temperature monitor circuit data is adjusted using the entered values.
摘要翻译：集成电路系统具有用于保持用于控制系统中的至少一个电路块的信息的参考数据表，并且还具有电源电路，体偏置控制电路，时钟传递电路，温度监视电路和 /或配置控制电路。通过在不同的电源电压，不同的体偏置电压，不同的时钟速度和/或不同的温度下测试系统来获得系统性能数据，来提高系统的性能。基于数据的值被输入到参考数据表中。使用输入的值来调整电源电路，主体偏置控制电路，时钟传送电路和/或温度监视器电路数据。

40. 发明申请

US20040024557A1 Control method of an automatic integrated circuit full testing system 有权
标题翻译：自动集成电路全面测试系统的控制方法
公开(公告)号：US20040024557A1
公开(公告)日：2004-02-05
申请号：US10368096
申请日：2003-02-18
发明人： Ming-Ren Chi , Peng-Chia Kuo
IPC分类号： G06F019/00 , G01R027/28 , G01R031/00 , G01R031/14 , G01L015/00 , G01M019/00
CPC分类号： G06F11/273 , G01R31/2893 , G01R31/319 , G06T7/0008 , G06T2207/30148
摘要： A control method for an automatic integrated circuit full testing system. A control device is utilized to control the testing process of the automatic integrated circuit full testing system. The steps for controlling the control device include driving an automatic transport device to fetch test integrated circuits from an integrated circuit supply rack to various testing computer stations. An automatic plug/unplug tool is driven so that each integrated circuit is plugged into the connector of a corresponding testing computer. All the testing computers are triggered to carry out respective preset testing programs. An image sensor is driven to monitor the an output image of the testing computers so that any abnormality in the integrated circuits can be determined. Thereafter, the automatic plug/unplug tool is driven to unload the tested integrated circuit from the testing computer. The automatic transport device is driven to transfer the tested integrated circuit to various integrated circuit bins of an integrated circuit binning device according to the testing results.
摘要翻译：一种自动集成电路全面测试系统的控制方法。控制装置用于控制自动集成电路全面测试系统的测试过程。用于控制控制装置的步骤包括驱动自动传送装置以从集成电路供应架取得测试集成电路到各种测试计算机站。驱动自动插头/拔出工具，使每个集成电路插入对应的测试计算机的连接器。触发所有测试计算机执行相应的预设测试程序。驱动图像传感器来监视测试计算机的输出图像，从而可以确定集成电路中的任何异常。此后，驱动自动插拔/拔出工具，将测试的集成电路从测试计算机卸载。根据测试结果，自动传送装置被驱动以将测试的集成电路传送到集成电路装箱装置的各种集成电路板。

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