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31. 发明申请

US20070234154A1 SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS 有权
标题翻译：使用嵌入式命令扫描框架进行扫描测试
公开(公告)号：US20070234154A1
公开(公告)日：2007-10-04
申请号：US11670241
申请日：2007-02-01
申请人： Lee Whetsel
发明人： Lee Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/3172 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G01R31/318536 , G01R31/318572 , G01R31/318577
摘要： Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
摘要翻译：集成电路的测试是通过利用扫描帧输入移位寄存器，扫描帧输出移位寄存器，测试控制器和包括扫描输入，扫描时钟，测试使能和扫描输出的测试接口的测试架构实现的。输入到扫描帧输入移位寄存器的扫描帧包含测试激励数据部分和测试命令部分。从扫描帧输出移位寄存器输出的扫描帧包含测试响应数据部分和可选地用于输出其他数据的部分。输入扫描帧的命令部分控制测试架构以执行所需的测试操作。

32. 发明授权

US07256647B2 Method and apparatus for presetting an amplifier 失效
标题翻译：放大器预置的方法和装置
公开(公告)号：US07256647B2
公开(公告)日：2007-08-14
申请号：US11162098
申请日：2005-08-29
申请人： Albert A. DeBrita , Michael J. Lencioni
发明人： Albert A. DeBrita , Michael J. Lencioni
IPC分类号： H03F3/04
CPC分类号： H03F3/45179 , G01R31/318577 , H03F3/04 , H03F3/45237 , H03F2203/45366
摘要： An output of a common mode differential amplifier is initialized to a known state, which includes inputting a voltage to a network conductor of an electronic assembly, where the network conductor is coupled to a first input node of a first differential input of the amplifier. The amplifier is on an integrated circuit chip of the assembly and has a self-bias node. Circuitry of the amplifier normally adjusts to obtain an equilibrium voltage on the self-bias node in response to the inputted voltages. To initialize the amplifier output, however, preset circuitry on the integrated circuit chip overrides the normal equilibrium voltage on the self-bias node, forcing the self-bias node to a predetermined voltage regardless of the amplifier input voltages. In response, the amplifier produces an desired initial output state on a first output node of the amplifier.
摘要翻译：共模差分放大器的输出被初始化为已知状态，其包括向电子组件的网络导体输入电压，其中网络导体耦合到放大器的第一差分输入的第一输入节点。放大器位于组件的集成电路芯片上，并具有自偏压节点。放大器的电路通常进行调整，以响应于输入的电压来获得自偏压节点上的平衡电压。然而，为了初始化放大器输出，集成电路芯片上的预置电路将覆盖自偏压节点上的正常平衡电压，迫使自偏压节点达到预定电压，而与放大器输入电压无关。作为响应，放大器在放大器的第一输出节点上产生期望的初始输出状态。

33. 发明申请

US20070162805A1 AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL 有权
标题翻译：使用外部控制的低功率自动扫描分区
公开(公告)号：US20070162805A1
公开(公告)日：2007-07-12
申请号：US11684042
申请日：2007-03-09
申请人： Jayashree Saxena , Lee Whetsel
发明人： Jayashree Saxena , Lee Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/31721 , G01R31/318563 , G01R31/318575 , G01R31/318577 , G06F1/3234
摘要： Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
摘要翻译：扫描架构通常用于测试集成电路中的数字电路。本发明描述了一种使常规扫描架构适应于低功率扫描架构的方法。低功耗扫描架构保持常规扫描架构的测试时间，同时要求比传统扫描架构明显更低的运行能力。低功耗扫描架构对于IC /模具制造商是有利的，因为它允许并行测试嵌入在IC /管芯中的更多数量的电路（例如DSP或CPU核心电路），而不消耗IC /管芯内的太多功率。由于低功耗扫描架构降低了测试功耗，因此可以使用传统的扫描架构在先前可能的同时在晶圆上测试更多的裸片。这允许减少晶片测试时间，这降低了晶片上每个芯片的制造成本。

34. 发明授权

US07174492B1 AC coupled line testing using boundary scan test methodology 有权
标题翻译：交流耦合线路测试采用边界扫描测试方法
公开(公告)号：US07174492B1
公开(公告)日：2007-02-06
申请号：US09834506
申请日：2001-04-12
申请人： Sung Soo Chung , Sang Hyeon Baeg
发明人： Sung Soo Chung , Sang Hyeon Baeg
IPC分类号： G01R31/28
CPC分类号： G01R31/318577
摘要： Testing AC coupled interconnects using boundary scan test methodology. Specially designed AC boundary scan cells and boundary scan logic are used. These are compatible with IEEE Standard 1149.1 testing. An AC_EXTEST method is used to determine the reliability of the AC coupled interconnections. The method includes preloading the test stimulus, initiating the AC_EXTEST instruction, executing the instruction, transferring the instruction results, and evaluating the results. During the test, the TAP controllers of both the driving and receiving ICs are held in the Run-Test/Idle state for the time required to complete execution of the instruction. During this time, the driving IC is applying the AC test stimulus to the interconnections and the receiving IC is sampling the signal. The test may be repeated with different test data and may be run together with a DC EXTEST method to determine the reliability of both the AC and the DC coupled interconnections independently.
摘要翻译：使用边界扫描测试方法测试交流耦合互连。使用特殊设计的交流边界扫描单元和边界扫描逻辑。这些与IEEE标准1149.1测试兼容。 AC_EXTEST方法用于确定交流耦合互连的可靠性。该方法包括预加载测试激励，启动AC_EXTEST指令，执行指令，传送指令结果以及评估结果。在测试期间，驱动和接收IC的TAP控制器在完成执行指令所需的时间内保持在运行测试/空闲状态。在此期间，驱动IC正在对互连进行交流测试激励，接收IC对信号进行采样。测试可以用不同的测试数据重复，并且可以与DC EXTEST方法一起运行，以独立地确定AC和DC耦合互连的可靠性。

35. 发明授权

US07137054B2 System and apparatus for scanning integrated circuits with numerically controlled delay lines 有权
标题翻译：用数字控制的延迟线扫描集成电路的系统和设备
公开(公告)号：US07137054B2
公开(公告)日：2006-11-14
申请号：US10420165
申请日：2003-04-22
申请人： Anand Pande , Syed Mohammed Ali , Naresh Chandra Srinivas Koppineedi , Ravindra Bindus , Ramanujan K. Valmiki
发明人： Anand Pande , Syed Mohammed Ali , Naresh Chandra Srinivas Koppineedi , Ravindra Bindus , Ramanujan K. Valmiki
IPC分类号： G01R31/28
CPC分类号： G11C29/12015 , G01R31/318577 , G01R31/318594 , G11C2029/3202
摘要： A system and method for scan testing an NCDL and latches controlled by the NCDL is presented. The NCDL is controlled by control logic, a switch is used to control the latches by a clock signal that is not controlled by the control logic. A controllability circuit provides test vectors to, and controls, the NCDL. The outputs of the NCDL are observed by an observability circuit that captures the outputs of the NCDL.
摘要翻译：提出了一种用于扫描测试NCDL和由NCDL控制的锁存器的系统和方法。 NCDL由控制逻辑控制，开关用于通过不由控制逻辑控制的时钟信号来控制锁存器。可控性电路为NCDL提供测试向量和控制NCDL。 NCDL的输出由捕获NCDL输出的可观测电路观察。

36. 发明授权

US07088091B2 Testing a multi-channel device 有权
标题翻译：测试多通道设备
公开(公告)号：US07088091B2
公开(公告)日：2006-08-08
申请号：US10640913
申请日：2003-08-14
申请人： Salem Abdennadher
发明人： Salem Abdennadher
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/31723 , G01R31/318577
摘要： In one embodiment, a method includes routing first test data from a first channel of a device to a second channel of the device, and outputting the first test data from the second channel. The device, in one embodiment, may be a mixed signal device and the test data may be alternating current test data.
摘要翻译：在一个实施例中，一种方法包括将第一测试数据从设备的第一通道路由到设备的第二通道，并从第二通道输出第一测试数据。在一个实施例中，该装置可以是混合信号装置，并且测试数据可以是交流的测试数据。

37. 发明申请

US20050229056A1 Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC) 有权
标题翻译：用于比较集成电路（IC）中的功能和AC扫描测试之间的电路性能的电路和方法
公开(公告)号：US20050229056A1
公开(公告)日：2005-10-13
申请号：US10818866
申请日：2004-04-06
申请人： John Rohrbaugh , Jeffrey Rearick
发明人： John Rohrbaugh , Jeffrey Rearick
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318566 , G01R31/318577 , G01R31/31858
摘要： A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), comprises an IC logic element, a scan chain, and a calibration circuit comprising a first plurality of flip-flops and a combinational delay line. The calibration circuit operates in a functional test mode and in a scan test mode to determine a clock signal delay between the functional test mode and the scan test mode.
摘要翻译：用于确定与集成电路（IC）相关联的时钟的操作速度的电路和方法包括IC逻辑元件，扫描链和包括第一多个触发器和组合延迟线的校准电路。校准电路在功能测试模式和扫描测试模式下工作，以确定功能测试模式和扫描测试模式之间的时钟信号延迟。

38. 发明申请

US20050066243A1 Mechanism to enhance observability of integrated circuit failures during burn-in tests 有权
标题翻译：增强烧录测试期间集成电路故障的可观察性的机制
公开(公告)号：US20050066243A1
公开(公告)日：2005-03-24
申请号：US10667879
申请日：2003-09-22
申请人： Gordhan Barevadia , Anupama Agashe , Nikila Krishnamoorthy , Rubin Parekhji , Neil Simpson
发明人： Gordhan Barevadia , Anupama Agashe , Nikila Krishnamoorthy , Rubin Parekhji , Neil Simpson
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319 , G11C29/44
CPC分类号： G11C29/44 , G01R31/2856 , G01R31/318577 , G01R31/31905 , G11C2029/3202 , G11C2029/3602
摘要： A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are monitored during the burn-in tests to provide a mechanism for observing selective scan chain outputs and memory BIST status outputs.
摘要翻译：系统和方法提高了老化测试期间IC故障的可观察性。扫描自动测试模式生成和内存自检模式在老化测试期间被监控，以提供观察选择性扫描链输出和存储器BIST状态输出的机制。

39. 发明申请

US20040153919A1 Signal pin tester for AC defects in integrated circuits 失效
标题翻译：集成电路中交流缺陷的信号针测试仪
公开(公告)号：US20040153919A1
公开(公告)日：2004-08-05
申请号：US10420431
申请日：2003-04-21
发明人： Frank W. Angelotti , Louis B. Bushard , Matthew S. Grady , Scott A. Strissel
IPC分类号： G01R031/28
CPC分类号： G01R31/318577
摘要： A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins so that when a selected data string is introduced into the integrated circuit so that each input/output pin on a data storage device in the integrated circuit will be tested in sequence whereby the number of contacts required by the tester can be reduced.
摘要翻译：一种测试装置和方法，用于通过在所述触点的子集中提供将每个相应的各个测试触点耦合到选择的接口来测试用于交流（AC）缺陷的集成电路的数据存储装置的输入/输出信号引脚多个数据存储输入/输出信号引脚，使得当选择的数据串被引入到集成电路中，使得集成电路中的数据存储设备上的每个输入/输出引脚将被依次测试，从而所需的触点数量由测试仪可以减少。

40. 发明申请

US20040128635A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20040128635A1
公开(公告)日：2004-07-01
申请号：US10736673
申请日：2003-12-17
发明人： Ryusuke Sahara , Kozaburo Kurita , Yuuji Suzuki , Mitsugu Kusunoki , Hideki Sakakibara
IPC分类号： G06F009/45
CPC分类号： G01R31/318577
摘要： The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal. A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.
摘要翻译：本发明提供一种配备有至少一个脉冲发生器的半导体集成电路器件，该脉冲发生器产生的脉冲脉冲短于传输信号的全幅度的上升时间。通过第一信号路径和第二信号路径从外部提供的第一信号和第二信号分别传送到脉冲发生器。当在第一信号路径和第二信号路径中的任何一个缓冲器上的上升时间达到全幅度时，脉冲发生器将形成的脉冲的脉冲宽度大于第一信号与第二信号路径之间的相位差使第二信号对应于第一脉冲的脉冲宽度。

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