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31. 发明授权

US07995645B2 Apparatus for measuring in-phase and quadrature (IQ) imbalance 有权
标题翻译：用于测量同相和正交（IQ）不平衡的装置
公开(公告)号：US07995645B2
公开(公告)日：2011-08-09
申请号：US12027762
申请日：2008-02-07
申请人： Kyeongho Lee , Joonbae Park , Jeong Woo Lee , Seung-Wook Lee , Eal Wan Lee
发明人： Kyeongho Lee , Joonbae Park , Jeong Woo Lee , Seung-Wook Lee , Eal Wan Lee
IPC分类号： H04B3/46
CPC分类号： H03D7/166 , H03D3/009 , H04L25/061 , H04L27/364 , H04L27/3863 , H04L2027/0016
摘要： The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a signal generator can provide a first IQ signal of a DC component during a first period and the first IQ signal of a first angular frequency during a second period, an IQ up-conversion mixer can up-convert the first IQ signal by a second angular frequency during the first period and up-convert the first IQ signal by a third angular frequency during the second period to output a second IQ signal, an IQ down-conversion mixer can down-convert the second IQ signal by the third angular frequency to output a third IQ signal and an IQ imbalance detector can obtain a first IQ imbalance (e.g., Rx IQ imbalance) from the third IQ signal during the first period and a second IQ imbalance (e.g., Tx/Rx IQ imbalance) during the second period.
摘要翻译：本总体发明构思涉及用于测量同相和正交（IQ）不平衡的装置和/或方法。在一个实施例中，信号发生器可以在第一周期期间提供DC分量的第一IQ信号，并且在第二周期期间提供第一角频率的第一IQ信号，IQ上变频混频器可以上变频第一IQ信号在第一周期期间以第二角度频率进行第二角度频率，并且在第二周期期间将第一IQ信号上升转换第三角度频率以输出第二IQ信号，IQ降频转换混频器可以将第二IQ信号下变频第三IQ信号输出第三IQ信号和IQ不平衡检测器的角频率可以在第一周期期间从第三IQ信号和第二IQ不平衡（例如，Tx / Rx IQ不平衡）获得第一IQ不平衡（例如，Rx IQ不平衡）第二期。

32. 发明授权

US07953192B2 Receiver with fast gain control and digital signal processing unit with transient signal compensation 有权
标题翻译：具有快速增益控制的接收器和具有瞬态信号补偿的数字信号处理单元
公开(公告)号：US07953192B2
公开(公告)日：2011-05-31
申请号：US11907960
申请日：2007-10-18
申请人： Suk Kyun Hong , Jae Ho Ryu , Sung Woo Ryu
发明人： Suk Kyun Hong , Jae Ho Ryu , Sung Woo Ryu
IPC分类号： H04L27/08
CPC分类号： H03G3/3068
摘要： Embodiments of the present general inventive concept relate to a transient signal compensator for apparatuses such as a transceiver or receiver used in a wire/wireless communication and/or a digital signal processor that may be used in the receiver and methods thereof. In one embodiment, a receiver can include an amplifier to amplify a received signal, a digital filter to filter a digital signal corresponding to an output signal of the amplifier, where the digital filter is configured to replace a corresponding value (e.g., stored in a memory) for the digital filter with a gain compensated value during a predetermined delay time after a gain of the amplifier is changed (e.g., from a first gain g1 to a different second gain g2). The gain compensated value to compensate for a transient signal (e.g., related to the change from the first gain g1 to the second gain g2).
摘要翻译：本发明总体构思的实施例涉及用于诸如在有线/无线通信中使用的收发器或接收器的装置的瞬时信号补偿器和/或可用于接收器的数字信号处理器及其方法。在一个实施例中，接收机可以包括用于放大接收信号的放大器，数字滤波器以对与放大器的输出信号相对应的数字信号进行滤波，其中数字滤波器被配置为替换对应的值（例如，存储在存储器），用于在放大器的增益改变（例如，从第一增益g1到不同的第二增益g2）之后的预定延迟时间期间具有增益补偿值的数字滤波器。增益补偿值以补偿瞬态信号（例如，与从第一增益g1到第二增益g2的变化相关）。

33. 发明授权

US07952435B2 Phase locked loop and method for compensating temperature thereof 有权
标题翻译：锁相环及其温度补偿方法
公开(公告)号：US07952435B2
公开(公告)日：2011-05-31
申请号：US11976912
申请日：2007-10-29
申请人： Seung-Wook Lee , Joonbac Park , Jeong Woo Lee , Su Won Kang , Kyeongho Lee
发明人： Seung-Wook Lee , Joonbac Park , Jeong Woo Lee , Su Won Kang , Kyeongho Lee
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L1/026 , H03L7/113 , H03L7/187
摘要： Embodiments of a phase lock loop and a method for compensating a temperature thereof can output an initial tuning digital value for a voltage controlled oscillator configured to output a desired phase lock loop frequency compensated according to a temperature change. Embodiments of a phase lock loop and a method for compensating a temperature thereof can simultaneously perform a digital coarse tuning and an analog fine tuning to compensate for a temperature in a limited time.
摘要翻译：锁相环的实施例和用于补偿其温度的方法可以输出用于输出根据温度变化补偿的期望锁相环的压控振荡器的初始调谐数字值。锁相环的实施例和用于补偿其温度的方法可以同时进行数字粗调和模拟微调以在有限的时间内补偿温度。

34. 发明授权

US07071535B2 Integrated circuit package having inductance loop formed from a bridge interconnect 有权
标题翻译：集成电路封装，其具有由桥互连形成的电感环路
公开(公告)号：US07071535B2
公开(公告)日：2006-07-04
申请号：US10927152
申请日：2004-08-27
申请人： Yido Koo , Hyungki Huh , Kang Yoon Lee , Jeong-Woo Lee , Joonban Park , Kyeongho Lee
发明人： Yido Koo , Hyungki Huh , Kang Yoon Lee , Jeong-Woo Lee , Joonban Park , Kyeongho Lee
IPC分类号： H01L29/00 , H03B7/14
CPC分类号： H01L23/642 , H01L23/645 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/48091 , H01L2224/48247 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.
摘要翻译：集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一引线和将芯片上的第二接合焊盘连接到第二引线的第二引线形成封装的I / O引脚。为了完成电感环路，第一和第二I / O引脚通过引脚之间的导电桥连接。可以通过使I / O引脚具有单一结构来形成桥。在另一个实施例中，桥由位于封装衬底的表面上或在该衬底内的金属化层形成。 I / O引脚优选为彼此相邻的引脚; 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

35. 发明授权

US07002410B2 Adaptive linearization technique for communication building block 有权
公开(公告)号：US07002410B2
公开(公告)日：2006-02-21
申请号：US10229267
申请日：2002-08-28
申请人： Hei-sam Jeong , Joonbae Park , Kyeongho Lee
发明人： Hei-sam Jeong , Joonbae Park , Kyeongho Lee
IPC分类号： H03F1/26
CPC分类号： H03F1/3223 , H03F1/3229
摘要： The present invention is directed to a linearization apparatus and method. Preferred embodiments according to the present invention can combine an auxiliary non-linear block to a functional block of a system to increase linearity of an output signal of the system such as a communication system. System overhead due to the non-linear auxiliary block can be small because of circuit structure, cost and low consumption. Further, the non-linear auxiliary block can be designed so that no feedback path is required. Further preferred embodiments can use a feedback path without loss of stability by using a cancellation apparatus or process based on an averaging detection of the output signal. For example, a feedback loop can detect power leakage in a sideband caused by non-linearities of the communication system.

36. 发明申请

US20040131109A1 Bidirectional turbo ISI canceller-based DSSS receiver for high-speed wireless LAN 有权
标题翻译：用于高速无线LAN的基于双向turbo ISI消除器的DSSS接收机
公开(公告)号：US20040131109A1
公开(公告)日：2004-07-08
申请号：US10690629
申请日：2003-10-23
申请人： GCT Semiconductor, Inc.
发明人： Byoung-Hoon Kim , Suwon Kang , Bong Youl Cho , Kyeongho Lee
IPC分类号： H04B001/707
CPC分类号： H04B1/7097 , H04B1/7115 , H04L25/03171
摘要： A bidirectional turbo ISI canceller cancels precursor-ISI as well as postcursor-ISI in a received signal without incorporating a multiplicative feedforward equalization filter. This is accomplished by taking a three-step receiver design approach. In the first step, an optimal single-symbol RAKE receiver is designed to comprise a CMF, a codeword correlator bank, and an energy bias (EB) canceller under the assumption that no ISI is generated by preceding or trailing symbols. In a second step, a DFE is included for suppressing postcursor-ISI caused by a preceding symbol. Finally, a precursor ISI canceler is used to remove the remaining ISI caused by a trailing symbol. All three components may be integrated into a BTIC-based receiver applying turbo-iteration processing.
摘要翻译：双向turbo ISI消除器在接收信号中取消前体ISI以及后端ISI，而不需要并入前置均衡滤波器。这是通过采取三步接收机设计方法来实现的。在第一步中，假定不存在由先前或后面符号产生的ISI，最佳单符号RAKE接收机被设计为包括CMF，码字相关器组和能量偏置（EB）消除器。在第二步骤中，包括用于抑制由先前符号引起的后期ISI的DFE。最后，使用前驱体ISI消除器去除由尾随符号引起的剩余ISI。所有三个组件可以被集成到应用turbo迭代处理的基于BTIC的接收机中。

37. 发明申请

US20020186063A1 Phase lock loop (PLL) apparatus and method 有权
标题翻译：锁相环（PLL）装置及方法
公开(公告)号：US20020186063A1
公开(公告)日：2002-12-12
申请号：US10196479
申请日：2002-07-17
申请人： GCT Semiconductor, Inc.
发明人： Kyeongho Lee , Deog-Kyoon Jeong
IPC分类号： H03L007/06
CPC分类号： H04B1/403 , H03F2200/372 , H03H11/22 , H03H2011/0494 , H03K9/00 , H03L7/0891 , H03L7/0995 , H03L7/0996 , H03L7/1974 , H04B1/28 , H04B1/40
摘要： A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.
摘要翻译：提供了一种锁相环（PLL）及其使用方法，包括多反馈CMOS压控振荡器（VCO）和多相采样分数N预分频器。 PLL为单芯片CMOS射频（RF）通信系统提供了更高的性能特性。多反馈CMOS VCO在降低VCO信号的上升/下降时间的同时保持VCO信号的幅度。多反馈CMOS VCO进一步降低了电源噪声影响。多相采样分数N预分频器为CMOS VCO提供足够的带宽，同时保持光谱纯度并减少分数。多相采样分数N预分频器可以包括分频器，采样器电路，选择器电路和模块化计数器。

38. 发明申请

US20020030529A1 Mixer structure and method for using same 有权
标题翻译：搅拌机结构及使用方法
公开(公告)号：US20020030529A1
公开(公告)日：2002-03-14
申请号：US09985897
申请日：2001-11-06
申请人： GCT Semiconductor, Inc.
发明人： Kyeongho Lee , Deog-Kyoon Jeong
IPC分类号： G06G007/16
CPC分类号： H04B1/40 , H03D7/1441 , H03F2200/372 , H03H11/22 , H03H2011/0494 , H03K9/00 , H03L7/0891 , H03L7/0995 , H03L7/1974 , H04B1/28 , H04B1/403
摘要： A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.
摘要翻译：根据本发明的混合器结构及其使用方法包括多相混合器。 VCO包括多个差分延迟单元，以输出多个多相时钟信号。多相混频器可以包括负载电路，开关电路，降噪电路和输入电路。开关电路被耦合以接收多个多相时钟信号，并且包括分别耦合到负载电路的第一开关阵列和第二开关阵列。耦合到开关电路的降噪电路可以包括响应偏置电压的晶体管。输入电路包括接收输入信号的晶体管。第一开关阵列包括耦合在第一输出端子和第二节点之间的第一多个开关，并且第二开关阵列包括耦合在第二输出端子和第二节点之间的第二多个开关。优选地，多个开关中的每一个包括两对串联连接的晶体管，其中串联连接的晶体管并联耦合以为两个输入端口中的每一个提供对称电连接。混频器和使用它的方法可以是接收RF输入信号的单或双平衡混频器。

39. 发明授权

US09014289B2 Transmission method for dual digital signal through single antenna, transmitter for dual digital signal through single antenna and receiving method for dual digital signal through single antenna 有权
标题翻译：双数字信号通过单天线传输方式，双数字信号发射机通过单天线和双数字信号通过单天线接收方式
公开(公告)号：US09014289B2
公开(公告)日：2015-04-21
申请号：US14064196
申请日：2013-10-28
申请人： GCT Semiconductor, Inc.
发明人： Eal Wan Lee , Dae Hong Kim , Jeong Min Kim
IPC分类号： H04B7/02 , H04L25/08 , H04L27/26 , H04B7/04
CPC分类号： H04L27/26 , H04B7/028 , H04B7/0413 , H04J11/004 , H04L25/0204 , H04L27/0008 , H04L27/2601 , H04L27/3488 , H04L27/36
摘要： Disclosed is a method of transmitting dual digital signals through a single antenna. The method includes receiving, by a transmitter, a first data stream and a second data stream which use the same carrier frequency, modulating, by the transmitter, each of the first data stream and the second data stream, lowering, by the transmitter, a power level of the modulated second data stream, combining, by the transmitter, the modulated first data stream and the second data stream with the lowered power level, and transmitting, by the transmitter, the added first data stream and second data stream to a single antenna in the same channel.
摘要翻译：公开了通过单个天线发送双数字信号的方法。该方法包括由发射机接收使用相同载波频率的第一数据流和第二数据流，由发射机调制第一数据流和第二数据流中的每一个，由发射机降低调制的第二数据流的功率电平，由发射机组合调制的第一数据流和具有降低的功率电平的第二数据流，并且由发射机将添加的第一数据流和第二数据流发送到单个天线在同一通道。

40. 发明授权

US08229028B2 Apparatus for measuring IQ imbalance 有权
标题翻译： IQ不平衡测量装置
公开(公告)号：US08229028B2
公开(公告)日：2012-07-24
申请号：US12034627
申请日：2008-02-20
申请人： Kyeongho Lee , Joonbae Park , Jeong Woo Lee , Seung-Wook Lee , Eal Wan Lee
发明人： Kyeongho Lee , Joonbae Park , Jeong Woo Lee , Seung-Wook Lee , Eal Wan Lee
IPC分类号： H04K1/02
CPC分类号： H04L27/3863 , H04L27/364
摘要： The present invention relates to an apparatus and a method for measuring an in phase and quadrature (IQ) imbalance. One embodiment according to the present general inventive concept can provide a method for measuring a Tx IQ imbalance generated in an IQ up-conversion mixer and an Rx IQ imbalance generated in an IQ down-conversion mixer, that includes measuring a first IQ imbalance corresponding to a first combination of the Rx IQ imbalance with the Tx IQ imbalance, measuring a second IQ imbalance corresponding to a second combination of the Rx IQ imbalance with the Tx IQ imbalance and obtaining the Tx IQ imbalance and the Rx IQ imbalance from the first IQ imbalance and the second IQ imbalance.
摘要翻译：本发明涉及用于测量同相和正交（IQ）不平衡的装置和方法。根据本发明总体构思的一个实施例可以提供一种用于测量在IQ上变频混频器中产生的Tx IQ不平衡和在IQ下变频混频器中产生的Rx IQ不平衡的方法，其包括测量对应于 Rx IQ不平衡与Tx IQ不平衡的第一组合，测量对应于Rx IQ不平衡与Tx IQ不平衡的第二组合的第二IQ不平衡，并且从第一IQ不平衡获得Tx IQ不平衡和Rx IQ不平衡和第二个智商不平衡。

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