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31. 发明授权

US10301175B2 Method for manufacturing MEMS double-layer suspension microstructure, and MEMS infrared detector 有权
公开(公告)号：US10301175B2
公开(公告)日：2019-05-28
申请号：US15327902
申请日：2015-08-20
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Errong Jing
IPC分类号： B81B7/02 , B81C1/00 , G01J1/04 , G01J1/42 , G01J5/02
摘要： A method for manufacturing a MEMS double-layer suspension microstructure comprises steps of: forming a first film body on a substrate, and a cantilever beam connected to the substrate and the first film body; forming a sacrificial layer on the first film body and the cantilever beam; patterning the sacrificial layer located on the first film body to manufacture a recessed portion used for forming a support structure, the bottom of the recessed portion being exposed of the first film body; depositing a dielectric layer on the sacrificial layer; patterning the dielectric layer to manufacture a second film body and the support structure, the support structure being connected to the first film body and the second film body; and removing the sacrificial layer to obtain the MEMS double-layer suspension microstructure.

32. 发明授权

US10101225B2 Pressure sensor with light detection of diaphragm protrusion 有权
公开(公告)号：US10101225B2
公开(公告)日：2018-10-16
申请号：US15119311
申请日：2015-05-06
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Dongbiao Qian
IPC分类号： G01L1/24 , G01L1/04
摘要： Provided is a pressure sensor that includes a detection film that is arranged on a silicon substrate, detects a pressure applied to a surface thereof, and generates a protrusion deformation in response to the pressure. The pressure sensor also includes an optical transmitter and an optical detector that are arranged on the silicon substrate on opposite sides of the detection film and are located at a plane parallel to a plane comprising the detection film. The pressure sensor also includes a pressure calculation module that is connected to the optical detector and is used for acquiring light intensity data and calculating a pressure value according to the light intensity data. Also provided is a method of manufacturing the pressure sensor.

33. 发明申请

US20180188652A1 PHOTOLITHOGRAPHY METHOD AND SYSTEM BASED ON HIGH STEP SLOPE 审中-公开
公开(公告)号：US20180188652A1
公开(公告)日：2018-07-05
申请号：US15905969
申请日：2018-02-27
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Jiale SU
IPC分类号： G03F7/20 , G03F1/38
CPC分类号： G03F7/2035 , G03F1/38 , G03F7/203
摘要： A photolithography system based on a high step slope may include a depositing unit configured to manufacture a sacrificial layer having high step slope on a substrate. The system may also include a coating unit configured to coat a photoresist layer on the sacrificial layer by performing a spin-on PR coating process to form a photolithographic layer. The system may further include a photolithography unit configured to perform one or more photolithography processes to the photolithographic layer. The photolithography unit may comprise a plurality of masks of compensation patterns. The compensation pattern may comprise a slope-top compensation pattern and a slope compensation pattern.

34. 发明授权

US09954074B2 Insulated gate bipolar transistor and manufacturing method therefor 有权
公开(公告)号：US09954074B2
公开(公告)日：2018-04-24
申请号：US14902517
申请日：2014-07-22
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Xiaoshe Deng , Genyi Wang , Dongfei Zhou
IPC分类号： H01L29/66 , H01L29/40 , H01L29/739 , H01L29/06 , H01L29/10 , H01L21/02 , H01L21/265
CPC分类号： H01L29/66333 , H01L21/02233 , H01L21/26513 , H01L29/0619 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/7395
摘要： An insulated gate bipolar transistor and a manufacturing method therefor. The insulated gate bipolar transistor comprises a semiconductor substrate (1) of a first conductive type, which is provided with a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises a primitive cell area (2) and a terminal protection area (4) which is located outside the primitive cell area; a first semiconductor layer (5) of a first conductive type which is formed at the side of the first major surface of the semiconductor substrate (1), wherein the doping concentration of the first semiconductor layer (5) is higher than the doping concentration of the semiconductor substrate (1); and an insulated gate transistor unit which is formed at the side of the first major surface of the first semiconductor layer (5) in the primitive cell area, wherein the insulated gate transistor unit is conducted, a channel of a first conductive type is formed. Compared with the prior art, the present invention not only can improve the voltage resistance reliability of the insulted gate bipolar transistor, but also can reduce the forward conductive voltage drop of the insulated gate bipolar transistor.

35. 发明授权

US09947785B2 Junction field effect transistor and manufacturing method therefor 有权
公开(公告)号：US09947785B2
公开(公告)日：2018-04-17
申请号：US15318857
申请日：2015-06-30
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Guangtao Han , Guipeng Sun
IPC分类号： H01L29/66 , H01L29/78 , H01L29/40 , H01L29/47 , H01L29/10 , H01L29/49 , H01L29/423 , H01L29/06 , H01L29/808
CPC分类号： H01L29/7831 , H01L29/0607 , H01L29/0623 , H01L29/0649 , H01L29/1045 , H01L29/105 , H01L29/1066 , H01L29/1083 , H01L29/408 , H01L29/4238 , H01L29/47 , H01L29/4916 , H01L29/66484 , H01L29/66681 , H01L29/66901 , H01L29/782 , H01L29/808
摘要： The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.

36. 发明授权

US09902613B2 Positioning method in microprocessing process of bulk silicon 有权
公开(公告)号：US09902613B2
公开(公告)日：2018-02-27
申请号：US15315640
申请日：2015-08-19
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Errong Jing
IPC分类号： H01L21/00 , B81C3/00
CPC分类号： B81C3/004 , B81C1/00 , B81C1/00603 , B81C3/00 , B81C2203/051 , G03F9/00 , H01L21/68
摘要： A positioning method in a microprocessing process of bulk silicon comprises the steps of: fabricating, on a first surface of a first substrate (10), a first pattern (100), a stepper photo-etching machine alignment mark (200) for positioning the first pattern, and a double-sided photo-etching machine first alignment mark (300) for positioning the stepper photo-etching machine alignment mark; fabricating, on a second surface, opposite to the first surface, of the first substrate, a double-sided photo-etching machine second alignment mark (400) corresponding to the double-sided photo-etching machine first alignment mark; bonding a second substrate (20) on the first surface of the first substrate; performing thinning on a first surface of the second substrate; fabricating, on the first surface of the second substrate, a double-sided photo-etching machine third alignment mark (500) corresponding to the double-sided photo-etching machine second alignment mark; and finding, on the first surface of the second substrate by using the double-sided photo-etching machine third alignment mark, a corresponding position of the stepper photo-etching machine alignment mark.

37. 发明授权

US09666682B2 Reverse conduction insulated gate bipolar transistor (IGBT) manufacturing method 有权
公开(公告)号：US09666682B2
公开(公告)日：2017-05-30
申请号：US14902302
申请日：2014-09-02
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Wanli Wang , Xiaoshe Deng , Genyi Wang , Qiang Rui
IPC分类号： H01L29/66 , H01L29/739 , H01L29/06 , H01L21/268 , H01L21/324 , H01L29/417 , H01L29/08 , H01L21/265 , H01L21/308
CPC分类号： H01L29/66333 , H01L21/26513 , H01L21/268 , H01L21/308 , H01L21/3247 , H01L29/0657 , H01L29/0696 , H01L29/0834 , H01L29/41716 , H01L29/7395
摘要： A reverse conducting insulated gate bipolar transistor (IGBT) manufacturing method, comprising the following steps: providing a substrate having an IGBT structure formed on the front surface thereof; implanting P+ ions onto the back surface of the substrate; forming a channel on the back surface of the substrate through photolithography and etching processes; planarizing the back surface of the substrate through a laser scanning process to form P-type and N-type interval structures; and forming a back surface collector by conducting a back metalizing process on the back surface of the substrate. Laser scanning process can process only the back surface structure requiring annealing, thus solve the problem of the front surface structure of the reverse conducting IGBT restricting back surface annealing to a low temperature, improving the P-type and N-type impurity activation efficiency in the back surface structure of the reverse conducting IGBT, and enhancing the performance of the reverse conducting IGBT.

38. 发明授权

US09620615B2 IGBT manufacturing method 有权
公开(公告)号：US09620615B2
公开(公告)日：2017-04-11
申请号：US14902516
申请日：2014-07-29
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Xiaoshe Deng , Qiang Rui , Shuo Zhang , Genyi Wang
IPC分类号： H01L21/00 , H01L29/66 , H01L29/739 , H01L21/265 , H01L21/311 , H01L29/06
CPC分类号： H01L29/66333 , H01L21/26513 , H01L21/31111 , H01L29/0611 , H01L29/7395
摘要： An insulated gate bipolar transistor (IGBT) manufacturing method comprises the following steps: providing a semiconductor substrate of a first conducting type, the semiconductor substrate having a first major surface and a second major surface (100); forming a field-stop layer of a second conducting type on the first major surface of the semiconductor substrate (200); growing an oxide layer on the field-stop layer (300); removing the oxide layer from the field-stop layer (400); forming an epitaxial layer on the field-stop layer from which the oxide layer has been removed; and then manufacturing an IGBT on the epitaxial layer (600). Before regular manufacturing of an IGBT, the surface defects of a substrate material are eliminated as many as possible before epitaxy is formed, and the quality of an epitaxial layer is improved, thereby improving the quality of the whole IGBT.

39. 发明申请

US20170073224A1 MEMS-BASED METHOD FOR MANUFACTURING SENSOR 有权
标题翻译：基于MEMS的制造传感器的方法
公开(公告)号：US20170073224A1
公开(公告)日：2017-03-16
申请号：US15312146
申请日：2015-05-05
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Yonggang HU , Guoping ZHOU
IPC分类号： B81C1/00
CPC分类号： B81C1/00619 , B81C1/00 , B81C2201/0133 , B81C2201/0142
摘要： An MEMS-based method for manufacturing a sensor comprises the steps of: forming a shallow channel (120) and a support beam (140) on a front surface of a substrate (100); forming a first epitaxial layer (200) on the front surface of the substrate (100) to seal the shallow channel (120); forming a suspended mesh structure (160) below the first epitaxial layer (200); and forming a deep channel (180) at a position on a back surface of the substrate (100) corresponding to the shallow channel (120), so that the shallow channel (120) is in communication with the deep channel (180). In the Method of manufacturing a MEMS-based sensor, when a shallow channel is formed on a front surface, a support beam of a mass block is formed, so the etching of a channel is easier to control, the process is snore precise. and the uniformity and the homogeneity of the formed support beam are better.
摘要翻译：用于制造传感器的基于MEMS的方法包括以下步骤：在衬底（100）的前表面上形成浅沟道（120）和支撑梁（140）; 在所述衬底（100）的前表面上形成第一外延层（200）以密封所述浅沟道（120）; 在所述第一外延层（200）下方形成悬浮网状结构（160）; 以及在与所述浅通道（120）相对应的所述基板（100）的背表面上的位置处形成深通道（180），使得所述浅通道（120）与所述深通道（180）连通。在制造基于MEMS的传感器的方法中，当在前表面上形成浅沟道时，形成质量块的支撑梁，因此通道的蚀刻更易于控制，工艺打鼾精确。形成的支撑梁的均匀性和均匀性更好。

40. 发明授权

US09371224B2 Silicon etching method 有权
标题翻译：硅蚀刻法
公开(公告)号：US09371224B2
公开(公告)日：2016-06-21
申请号：US14411931
申请日：2013-09-03
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Jiale Su
IPC分类号： B81C1/00 , H01L21/308
CPC分类号： B81C1/00396 , B81B2203/033 , B81C1/00412 , B81C1/00619 , B81C1/00626 , B81C2201/0132 , H01L21/3086
摘要： A silicon etching method of etching a silicon substrate to form silicon trenches having different width dimensions includes: S1, providing a silicon substrate; S2, depositing a mask layer on the silicon substrate; S3, corroding the mask layer to form windows having different width dimensions, wherein a mask layer having a certain thickness is reserved at least at a bottom portion of a window having a non-minimum width dimension, such that all the silicon trenches have the same depth after step S4; and S4, corroding the mask layer at the bottom portion of the window and the silicon substrate to form the silicon trenches. The mask layer having a certain thickness is reserved at the bottom portion of the window having the non-minimum width dimension, a relatively large window is protected, and a relatively small window is etched first, so that the finally obtained silicon trenches have the same depth.
摘要翻译：蚀刻硅衬底以形成具有不同宽度尺寸的硅沟槽的硅蚀刻方法包括：S1，提供硅衬底; S2，在硅衬底上沉积掩模层; S3，腐蚀掩模层以形成具有不同宽度尺寸的窗口，其中具有一定厚度的掩模层至少在具有非最小宽度尺寸的窗口的底部保留，使得所有硅沟槽具有相同的步骤S4之后的深度; 和S4，腐蚀窗口底部的掩模层和硅衬底以形成硅沟槽。具有一定厚度的掩模层被保留在具有非最小宽度尺寸的窗口的底部，相对较大的窗口被保护，并且首先蚀刻相对小的窗口，使得最终获得的硅沟槽具有相同的深度。

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