专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20150243366A1 ONE TIME PROGRAMMABLE MEMORY CELL AND METHOD FOR PROGRAMING AND READING A MEMORY ARRAY COMPRISING THE SAME 有权
标题翻译：一个可编程存储器单元和用于编程和读取包含该存储器单元的存储器阵列的方法
公开(公告)号：US20150243366A1
公开(公告)日：2015-08-27
申请号：US14697652
申请日：2015-04-28
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Chih-Hao Huang , Hsin-Ming Chen
IPC分类号： G11C17/16 , H01L27/112 , H01L29/78 , G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/101 , H01L27/11206 , H01L27/11286 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.
摘要翻译：本发明提供一种包括选择栅极晶体管，随后的栅极晶体管和反熔丝变容二极管的一次性可编程（OTP）存储单元。选择栅极晶体管具有分别耦合到第一漏极端子和第一源极端子的第一栅极端子，第一漏极端子，第一源极端子和两个第一源极/漏极扩展区域。以下栅极晶体管具有分别耦合到第二漏极端子和第二源极端子的两个第二源极/漏极延伸区域的第二栅极端子，第二漏极端子，耦合到第一漏极端子的第二源极端子。反熔丝变容二极管具有第三栅极端子，第三漏极端子，耦合到第二漏极端子的第三源极端子和与第三漏极端子和第三源极端子耦合的第三源极/漏极扩展区域，用于短路第三漏极端子和第三源终端。

32. 发明授权

US11070383B2 Random code generator 有权
公开(公告)号：US11070383B2
公开(公告)日：2021-07-20
申请号：US16233454
申请日：2018-12-27
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Hsin-Ming Chen
IPC分类号： H04L9/32 , G06F21/71 , H04L9/06 , H04L9/08
摘要： A random code generator includes an address Y decoder, an address X decoder, a PUF entropy pool, a processing circuit and an entropy key storage circuit. The address Y decoder includes plural Y control lines. The address Y decoder selectively activates the plural Y control lines according to a first address Y signal. The address X decoder includes plural X control lines. The address X decoder selectively activates the plural X control lines according to a first address X signal. The PUF entropy pool generates an output data according to the activated Y control lines and the activated X control lines. When the random code generator is in a normal working state, the processing circuit processes the output data into a random code according to at least one entropy key from the entropy key storage circuit.

33. 发明申请

US20190165955A1 ANTI-COUNTERFEIT COMMUNICATION SYSTEM 审中-公开
公开(公告)号：US20190165955A1
公开(公告)日：2019-05-30
申请号：US16157098
申请日：2018-10-11
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Hsin-Ming Chen
IPC分类号： H04L9/32 , H04L29/06 , H04L9/30 , H04L9/08
摘要： The communication system includes a communication buffer and a communication terminal. The communication buffer includes a physical unclonable function (PUF) device, and the communication buffer provides a security key generated by the PUF device. The communication terminal is coupled to the communication buffer, and transmits a mapping request to the communication buffer to ask for the security key. The communication terminal manipulates the transmission data with the security key to generate the encrypted data, and transmits the encrypted data to the communication buffer. The communication buffer further restores the transmission data from the encrypted data according to the security key.

34. 发明申请

US20190081804A1 SECURITY SYSTEM WITH ENTROPY BITS 审中-公开
公开(公告)号：US20190081804A1
公开(公告)日：2019-03-14
申请号：US15915074
申请日：2018-03-08
申请人： eMemory Technology Inc.
发明人： Hsin-Ming Chen , Meng-Yi Wu , Po-Hao Huang
IPC分类号： H04L9/32 , G11C17/16 , G11C17/18 , H04L9/08
摘要： A security system with entropy bits includes a physically unclonable function circuit, and a security key generator. The physically unclonable function circuit provides a plurality of entropy bit strings. The security key generator generates a security key by manipulating a manipulation bit string derived from the plurality of entropy bit strings according to an operation entropy bit string. Each bit of the operation entropy bit string is used to determine whether to perform a corresponding operation to the manipulation bit string.

35. 发明申请

US20190079732A1 RANDOM CODE GENERATOR AND ASSOCIATED RANDOM CODE GENERATING METHOD 审中-公开
公开(公告)号：US20190079732A1
公开(公告)日：2019-03-14
申请号：US16111688
申请日：2018-08-24
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Hsin-Ming Chen
IPC分类号： G06F7/58 , H03K3/84
摘要： A random code generator is installed in a semiconductor chip and includes a PUF cell array, a control circuit and a verification circuit. The PUF cell array includes m×n PUF cells. The control circuit is connected with the PUF cell array. While a enroll action is performed, the control circuit enrolls the PUF cell array. The verification circuit is connected with the PUF cell array. While a verification action is performed, the verification circuit determines that p PUF cells of the PUF cell array are normal PUF cells and generates a corresponding a mapping information, wherein p is smaller than m×n. While the semiconductor chip is enabled, the control circuit reads states of the p normal PUF cells of the PUF cell array according to the mapping information and generates a random code according to the states.

36. 发明授权

US10090260B2 Semiconductor apparatus with fake functionality 有权
公开(公告)号：US10090260B2
公开(公告)日：2018-10-02
申请号：US15387609
申请日：2016-12-21
申请人： eMemory Technology Inc.
发明人： Hsin-Ming Chen , Lun-Chun Chen , Meng-Yi Wu , Chih-Hao Huang , Tung-Cheng Kuo
IPC分类号： H01L23/00 , H01L23/522 , H01L27/088 , H01L29/06 , G11C16/14 , H01L27/11507 , H01L27/11529 , H01L29/423 , G06F7/58 , G11C17/16 , G11C17/18 , G11C16/04 , H01L27/11558 , H01L49/02 , H01L29/78
摘要： A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device.

37. 发明授权

US09935113B2 Non-volatile memory and method for programming and reading a memory array having the same 有权
公开(公告)号：US09935113B2
公开(公告)日：2018-04-03
申请号：US15604672
申请日：2017-05-25
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Hsin-Ming Chen
IPC分类号： H01L27/112 , H01L29/78 , H01L23/525 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/165 , H01L29/16 , H01L29/423 , G11C17/16 , G11C17/18
CPC分类号： H02M3/07 , G11C5/145 , G11C5/147 , G11C7/06 , G11C7/062 , G11C7/065 , G11C7/12 , G11C7/18 , G11C7/22 , G11C11/419 , G11C17/165 , G11C17/18 , G11C2207/002 , H01L23/5252 , H01L27/11206 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/1608 , H01L29/165 , H01L29/42376 , H01L29/7848 , H01L29/7851 , H02M2003/075 , H03K3/012 , H03K5/134 , H03K5/159 , H03K17/687 , H03K2005/00195
摘要： A non-volatile memory (NVM) includes a fin structure, a first fin field effect transistor (FinFET), a second FinFET, an antifuse structure, a third FinFET, and a fourth FinFET. The antifuse structure is formed on the fin structure and has a sharing gate, a single diffusion break (SDB) isolation structure, a first source/drain region, and a second source/drain region. The SDB isolation structure isolates the first source/drain region and the second source/drain region. The first FinFET, the second FinFET and the first antifuse element compose a first one time programmable (OTP) memory cell, and the third FinFET, the fourth FinFET and the second antifuse element compose a second OTP memory cell. The first OTP memory cell and the second OTP memory cell share the antifuse structure.

38. 发明申请

US20170206980A1 METHOD FOR PROGRAMMING ANTIFUSE-TYPE ONE TIME PROGRAMMABLE MEMORY CELL 有权
公开(公告)号：US20170206980A1
公开(公告)日：2017-07-20
申请号：US15392348
申请日：2016-12-28
申请人： eMemory Technology Inc.
发明人： Wei-Zhe Wong , Hsin-Ming Chen
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/1076 , G06F12/1408 , G06F21/72 , G06F21/73 , G06F2212/1052 , G06F2212/402 , G11C5/063 , G11C7/10 , G11C7/22 , G11C7/24 , G11C16/0408 , G11C16/08 , G11C16/22 , G11C16/24 , G11C16/26 , G11C16/32 , G11C17/16 , G11C29/785 , H01L27/11206 , H03K3/356113 , H04L9/3278
摘要： A method for programming an antifuse-type OTP memory cell is provided. Firstly, a first program voltage is provided to a gate terminal of an antifuse transistor. A first bit line voltage is transmitted to the antifuse transistor. A first voltage stress with a first polarity is provided to a gate oxide layer of the antifuse transistor to form a weak path between the gate terminal and the first drain/source terminal of the antifuse transistor. Secondly, a second program voltage is provided to the gate terminal of the antifuse transistor. A second bit line voltage is transmitted to the antifuse transistor. A second voltage stress with a second polarity is provided to the gate oxide layer of the antifuse transistor. Consequently, a program current is generated along the weak path to rupture the gate oxide layer above the first drain/source terminal.

39. 发明申请

US20160104542A1 MEMORY CELL CAPABLE OF OPERATING UNDER LOW VOLTAGE CONDITIONS 有权
标题翻译：在低电压条件下运行的存储单元
公开(公告)号：US20160104542A1
公开(公告)日：2016-04-14
申请号：US14798478
申请日：2015-07-14
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Chih-Hao Huang , Hsin-Ming Chen
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18 , G11C16/0408 , G11C16/0433 , G11C16/08 , G11C16/10 , G11C16/14 , G11C17/16 , G11C29/785 , H01L23/5252 , H01L23/5256 , H01L27/10897 , H01L27/1116 , H01L27/11206 , H01L27/11524 , H01L27/1156 , H01L29/0649 , H01L29/1033 , H01L29/78 , H01L29/8611 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A memory cell includes a programming selection transistor, a following gate transistor, an antifuse element, and a reading circuit. A charging current formed by the antifuse element may trigger the reading circuit to form a stable read current during a reading operation of the memory cell so that the time for reading data from the memory cell can be shortened. A discharging process may be operated in the beginning of the reading operation of the memory cell so that the window of time for reading data from the memory cell can be widened.
摘要翻译：存储单元包括编程选择晶体管，随后的栅极晶体管，反熔丝元件和读取电路。由反熔丝元件形成的充电电流可以在存储单元的读取操作期间触发读取电路形成稳定的读取电流，从而可以缩短从存储单元读取数据的时间。可以在存储单元的读取操作开始时进行放电处理，从而可以扩大从存储单元读取数据的时间窗口。

40. 发明授权

US09099392B2 Method of fabricating erasable programmable single-poly nonvolatile memory 有权
标题翻译：制造可擦除可编程单一多晶硅非易失性存储器的方法
公开(公告)号：US09099392B2
公开(公告)日：2015-08-04
申请号：US13941814
申请日：2013-07-15
申请人： eMemory Technology Inc.
发明人： Te-Hsun Hsu , Hsin-Ming Chen , Wen-Hao Ching , Wei-Ren Chen
IPC分类号： H01L21/28 , H01L29/40 , H01L27/115
CPC分类号： H01L21/28 , H01L27/11558 , H01L27/1156 , H01L29/401
摘要： The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.
摘要翻译：本发明提供一种制造可擦除可编程单多晶非易失性存储器的方法，包括以下步骤：在第一类型衬底中限定第一区域和第二区域; 在所述第一区域中形成第二类型井区域; 形成覆盖所述第一区域的表面的第一栅极氧化物层和第二栅极氧化物层，其中所述第二栅极氧化物层延伸到所述第二区域并邻近所述第二区域; 在第二区域中形成DDD区域; 在所述第二区域上方蚀刻所述第二栅极氧化物层的一部分; 形成覆盖所述第一和第二栅极氧化物层的两个多晶硅栅极; 以及限定所述DDD区域中的第二类型掺杂区域并限定所述第二类型阱区域中的第一类型掺杂区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式