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31. 发明申请

US20070190671A1 Manufacturing method of semiconductor integrated circuit device and probe card 有权
标题翻译：半导体集成电路器件和探针卡的制造方法
公开(公告)号：US20070190671A1
公开(公告)日：2007-08-16
申请号：US11783778
申请日：2007-04-12
申请人： Masayoshi Okamoto , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Akira Shimase
发明人： Masayoshi Okamoto , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Akira Shimase
IPC分类号： H01L21/66
CPC分类号： G01R3/00 , G01R1/07307
摘要： Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.
摘要翻译：电测试将在形成测试焊盘的半导体集成电路器件上进行。为了便于这种测试，半导体集成电路器件的制造方法采用具有两个或更多个能够接触两个或更多个电极的接触端子的探针卡。该探针卡与形成有第一布线的半导体集成电路器件的布线基板相对应，具有接触两个以上的电极的两个以上的接触端子的第一片; 电连接到所述两个或更多个接触端子和所述第一布线的第二布线; 并且在两个或多个接触端子的形成区域附近的第一虚拟布线被布置到第二布线的非形成区域，并且不参与信号传递。

32. 发明申请

US20050227383A1 Manufacturing method of semiconductor integrated circuit device and probe card 有权
标题翻译：半导体集成电路器件和探针卡的制造方法
公开(公告)号：US20050227383A1
公开(公告)日：2005-10-13
申请号：US11100600
申请日：2005-04-07
申请人： Masayoshi Okamoto , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Akira Shimase
发明人： Masayoshi Okamoto , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Akira Shimase
IPC分类号： G01R31/26 , G01R1/067 , G01R1/073 , G01R3/00 , H01L21/66 , H01L21/82
CPC分类号： G01R3/00 , G01R1/07307
摘要： Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.
摘要翻译：电测试将在形成测试焊盘的半导体集成电路器件上进行。为了便于这种测试，半导体集成电路器件的制造方法采用具有两个或更多个能够接触两个或更多个电极的接触端子的探针卡。该探针卡包括与形成有第一布线的半导体集成电路器件的布线基板相对的第一片，具有两个或更多个接触端子以与两个或更多个电极接触的第一片; 电连接到所述两个或更多个接触端子和所述第一布线的第二布线; 并且在两个或多个接触端子的形成区域附近的第一虚拟布线被布置到第二布线的非形成区域，并且不参与信号传递。

33. 发明授权

US07688086B2 Fabrication method of semiconductor integrated circuit device and probe card 失效
标题翻译：半导体集成电路器件和探针卡的制造方法
公开(公告)号：US07688086B2
公开(公告)日：2010-03-30
申请号：US11555993
申请日：2006-11-02
申请人： Yasuhiro Motoyama , Yoshimi Horigome , Seigo Nakamura , Iwao Natori
发明人： Yasuhiro Motoyama , Yoshimi Horigome , Seigo Nakamura , Iwao Natori
IPC分类号： G01R31/02
CPC分类号： G01R1/07314
摘要： To provide a technique of firmly bringing a stylus and a test pad into contact with each other in carrying out a probe testing summarizingly for plural chips by using a prober having the stylus formed by a technique of manufacturing a semiconductor integrated circuit device, plane patterns of respective wirings are formed such that a wiring and a wiring electrically connected to the wiring or a wiring which is not electrically connected to the wiring overlap each other, and a plane pattern arranged with both of the wiring and the wiring is constituted at upper portions of probes. Further, patterns of the wirings are formed such that an interval of arranging the wirings and a density of arranging the wirings become uniform at respective wiring layers in a thin film sheet.
摘要翻译：为了提供一种牢固地使触针和测试垫彼此接触的技术，通过使用具有通过制造半导体集成电路器件的技术形成的触针的探针来对多个芯片进行总体测试测试，其平面图案各布线形成为使布线和与布线电连接的布线或与布线不电连接的布线重叠，并且布置在布线和布线两者中的平面图形被构成在探针。此外，布线的图案形成为使得布线布置的间隔和布线的密度在薄膜片的各个布线层处变得均匀。

34. 发明申请

US20070108997A1 FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROBE CARD 失效
标题翻译：半导体集成电路器件和探针卡的制造方法
公开(公告)号：US20070108997A1
公开(公告)日：2007-05-17
申请号：US11555993
申请日：2006-11-02
申请人： Yasuhiro Motoyama , Yoshimi Horigome , Seigo Nakamura , Iwao Natori
发明人： Yasuhiro Motoyama , Yoshimi Horigome , Seigo Nakamura , Iwao Natori
IPC分类号： G01R31/02
CPC分类号： G01R1/07314
摘要： To provide a technique of firmly bringing a stylus and a test pad into contact with each other in carrying out a probe testing summarizingly for plural chips by using a prober having the stylus formed by a technique of manufacturing a semiconductor integrated circuit device, plane patterns of respective wirings are formed such that a wiring and a wiring electrically connected to the wiring or a wiring which is not electrically connected to the wiring overlap each other, and a plane pattern arranged with both of the wiring and the wiring is constituted at upper portions of probes. Further, patterns of the wirings are formed such that an interval of arranging the wirings and a density of arranging the wirings become uniform at respective wiring layers in a thin film sheet.
摘要翻译：为了提供一种牢固地使触针和测试垫彼此接触的技术，通过使用具有通过制造半导体集成电路器件的技术形成的触针的探针来对多个芯片进行总体测试测试，其平面图案各布线形成为使布线和与布线电连接的布线或与布线不电连接的布线重叠，并且布置在布线和布线两者中的平面图形被构成在探针。此外，布线的图案形成为使得布线布置的间隔和布线的密度在薄膜片的各个布线层处变得均匀。

35. 发明申请

US20120064646A1 METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20120064646A1
公开(公告)日：2012-03-15
申请号：US13228334
申请日：2011-09-08
申请人： Seigo NAKAMURA , Iwao Natori , Yasuhiro Motoyama
发明人： Seigo NAKAMURA , Iwao Natori , Yasuhiro Motoyama
IPC分类号： H01L21/66
CPC分类号： G01R31/2889 , G01R1/07314 , G01R1/0735
摘要： The variation in the contact pressures of the plurality of contact terminals to the plurality of chip electrodes is decreased. A thin-film sheet (first sheet) includes: a principal surface (contact-terminal formation surface) on which a plurality of contactors (contact terminals) are formed; and a rear surface positioned on an opposite side to the principal surface. Also, in the thin film sheet, a plurality of wirings and dummy wiring are arranged between the principal surface and the rear surface. A slit formed of an opening portion penetrating from the principal surface of the thin-film sheet to the rear surface thereof is formed along the wiring between the dummy wiring and the contactor arranged at an end of a contactor group (first contact terminal group) in which the plurality of contactors are aligned.
摘要翻译：多个接触端子对多个芯片电极的接触压力的变化减小。薄膜片（第一片）包括：形成有多个接触器（接触端子）的主表面（接触端子形成表面）; 以及位于与主表面相对的一侧的后表面。此外，在薄膜片中，在主面和背面之间配置有多根配线和虚设布线。沿着布置在接触器组（第一接触端子组）的端部处的虚设布线和接触器之间的布线，形成有从薄膜片的主表面贯穿其后表面的开口部分形成的狭缝，多个接触器对齐。

36. 发明授权

US08323992B2 Method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US08323992B2
公开(公告)日：2012-12-04
申请号：US13228334
申请日：2011-09-08
申请人： Seigo Nakamura , Iwao Natori , Yasuhiro Motoyama
发明人： Seigo Nakamura , Iwao Natori , Yasuhiro Motoyama
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： G01R31/2889 , G01R1/07314 , G01R1/0735
摘要： The variation in the contact pressures of the plurality of contact terminals to the plurality of chip electrodes is decreased. A thin-film sheet (first sheet) includes: a principal surface (contact-terminal formation surface) on which a plurality of contactors (contact terminals) are formed; and a rear surface positioned on an opposite side to the principal surface. Also, in the thin film sheet, a plurality of wirings and dummy wiring are arranged between the principal surface and the rear surface. A slit formed of an opening portion penetrating from the principal surface of the thin-film sheet to the rear surface thereof is formed along the wiring between the dummy wiring and the contactor arranged at an end of a contactor group (first contact terminal group) in which the plurality of contactors are aligned.
摘要翻译：多个接触端子对多个芯片电极的接触压力的变化减小。薄膜片（第一片）包括：形成有多个接触器（接触端子）的主表面（接触端子形成表面）; 以及位于与主表面相对的一侧的后表面。此外，在薄膜片中，在主面和背面之间配置有多根配线和虚设布线。沿着布置在接触器组（第一接触端子组）的端部处的虚设布线和接触器之间的布线，形成有从薄膜片的主表面贯穿其后表面的开口部分形成的狭缝，多个接触器对齐。

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