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31. 发明授权

US07483548B2 Method for detecting object formed of regions from image 有权
标题翻译：从图像中检测由区域形成的物体的方法
公开(公告)号：US07483548B2
公开(公告)日：2009-01-27
申请号：US10452426
申请日：2003-06-02
申请人： Yuusuke Nakano , Youichi Kawakami , Daisaku Horie , Yuichi Kawakami
发明人： Yuusuke Nakano , Youichi Kawakami , Daisaku Horie , Yuichi Kawakami
IPC分类号： G06K9/00 , G06K9/68
CPC分类号： G06K9/00362 , G06K9/00228
摘要： An apparatus for detecting a person or the like from an image extracts candidates, which are considered to human body regions, from the image. Region likelihood probabilities of the respective candidates are obtained, and a human body likelihood of a collection of the candidates is probabilistically calculated using the region likelihood probabilities and correlations among the candidates. It is thereby possible to detect the person robustly against occlusion or change in photographic environment without increasing calculation cost.
摘要翻译：从图像中检测人物等的装置从图像中提取被认为是人体区域的候选物。获得各个候选的区域似然概率，并且使用候选之间的区域似然概率和相关性来概率地计算候选人的收集的人体可能性。因此，可以在不增加计算成本的情况下鲁棒地检测人物抵抗摄影环境中的遮挡或变化。

32. 发明授权

US07221779B2 Object measuring apparatus, object measuring method, and program product 有权
标题翻译：物体测量装置，物体测量方法和程序产品
公开(公告)号：US07221779B2
公开(公告)日：2007-05-22
申请号：US10953976
申请日：2004-09-29
申请人： Yuichi Kawakami , Yuusuke Nakano
发明人： Yuichi Kawakami , Yuusuke Nakano
IPC分类号： G06K9/03 , H04N9/24 , G02B9/02
CPC分类号： G06M11/00 , G07C9/00
摘要： The present invention provides an object measuring apparatus capable of performing high-speed process and accurately counting the number of a plurality of objects even in the case where the plurality of objects pass a boundary line simultaneously. The object measuring apparatus extracts motion vectors at a plurality of times in each of a plurality of positions on a boundary line on the basis of a plurality of images. The object measuring apparatus obtains at least one integral value by integrating components perpendicular to the boundary line of the motion vectors. As the at least one integral value, for example, an integral value derived by integrating the perpendicular components of one of positive and negative signs is obtained. The object measuring apparatus calculates the number of moving objects (people and the like) passing the boundary line on the basis of the integral value.
摘要翻译：本发明提供一种即使在多个物体同时通过边界线的情况下，也能够进行高速处理并且准确地计数多个物体的数量的物体测量装置。物体测量装置基于多个图像在边界线上的多个位置中的每一个中多次提取运动矢量。物体测量装置通过对垂直于运动矢量的边界线的分量进行积分而获得至少一个积分值。作为至少一个积分值，例如，获得通过积分正负符号之一的垂直分量而导出的积分值。物体测量装置基于积分值计算通过边界线的移动物体（人物等）的数量。

33. 发明申请

US20050084133A1 Object measuring apparatus, object measuring method, and program product 有权
标题翻译：物体测量装置，物体测量方法和程序产品
公开(公告)号：US20050084133A1
公开(公告)日：2005-04-21
申请号：US10953976
申请日：2004-09-29
申请人： Yuichi Kawakami , Yuusuke Nakano
发明人： Yuichi Kawakami , Yuusuke Nakano
IPC分类号： G06T1/00 , G06K9/00 , G06M11/00 , G06T7/20 , G06T7/60 , G07C9/00
CPC分类号： G06M11/00 , G07C9/00
摘要： The present invention provides an object measuring apparatus capable of performing high-speed process and accurately counting the number of a plurality of objects even in the case where the plurality of objects pass a boundary line simultaneously. The object measuring apparatus extracts motion vectors at a plurality of times in each of a plurality of positions on a boundary line on the basis of a plurality of images. The object measuring apparatus obtains at least one integral value by integrating components perpendicular to the boundary line of the motion vectors. As the at least one integral value, for example, an integral value derived by integrating the perpendicular components of one of positive and negative signs is obtained. The object measuring apparatus calculates the number of moving objects (people and the like) passing the boundary line on the basis of the integral value.
摘要翻译：本发明提供一种即使在多个物体同时通过边界线的情况下，也能够进行高速处理并且准确地计数多个物体的数量的物体测量装置。物体测量装置基于多个图像在边界线上的多个位置中的每一个中多次提取运动矢量。物体测量装置通过对垂直于运动矢量的边界线的分量进行积分而获得至少一个积分值。作为至少一个积分值，例如，获得通过积分正负符号之一的垂直分量而导出的积分值。物体测量装置基于积分值计算通过边界线的移动物体（人物等）的数量。

34. 发明授权

US4811268A Processing circuit capable of raising throughput of accumulation 失效
标题翻译：处理电路能够提高积累的吞吐量
公开(公告)号：US4811268A
公开(公告)日：1989-03-07
申请号：US864268
申请日：1986-05-19
申请人： Takao Nishitani , Yuichi Kawakami
发明人： Takao Nishitani , Yuichi Kawakami
IPC分类号： G06F7/544 , G06F17/10 , G06F7/38 , G06F7/52
CPC分类号： G06F7/5443 , G06F17/10 , G06F7/49921
摘要： In a processing circuit for successively accumulating a first predetermined number of products, each product is shifted in a barrel shifter (20) downwards by a second predetermined number of bits determined in relation to the first predetermined number and is successively added to a previous result of accumulation in an arithmetic/logic unit (ALU) (21) the first predetermined number of times to produce a final result of accumulation. The first result is shifted in a shifter (27) upwards by a third predetermined number of bits determined in relation to the second predetermined number. An overflow detector (26) monitors each result of accumulation to detect occurrence of an overflow in the ALU and the shifter to substitute either a positive or a negative maximum number for each result by an overflow corrector (25) on occurrence of the overflow. The substituted maximum number or the shifted final result is produced as an output signal.
摘要翻译：在用于连续地累积第一预定数量的乘积的处理电路中，每个乘积在桶形移位器（20）中向下移动相对于第一预定数量确定的第二预定数量的位，并被连续地添加到在算术/逻辑单元（ALU）（21）中积累第一预定次数以产生累积的最终结果。第一结果在移位器（27）中向上移动相对于第二预定数确定的第三预定数量的位。溢出检测器（26）监视每个累积结果，以检测ALU和移位器中的溢出的发生，以便在出现溢出时由溢出校正器（25）替换每个结果的正或负最大数目。取代的最大数量或移位的最终结果作为输出信号产生。

35. 发明授权

US4722068A Double precision multiplier 失效
标题翻译：双精度乘法器
公开(公告)号：US4722068A
公开(公告)日：1988-01-26
申请号：US727020
申请日：1985-04-25
申请人： Ichiro Kuroda , Takao Nishitani , Hideo Tanaka , Yuichi Kawakami
发明人： Ichiro Kuroda , Takao Nishitani , Hideo Tanaka , Yuichi Kawakami
IPC分类号： G06F7/533 , G06F7/00 , G06F7/52 , G06F7/53 , G06F7/76
CPC分类号： G06F7/5324 , G06F2207/382
摘要： A double precision multiplyer for performing the multiplication of two double precision data using a 2's complement single precision multiplier. The 2n-1 bit double precision data is divided into one single precision data formed by taking the upper n bits of the double precision data and another single precision data formed by adding a "0" bit before the most significant bit of the remaining n-1 bits of the double precision data. Apparatus for performing the double precision multiplication thereby eliminates the necessity of discriminating the sign bit and enhances the speed of the double precision multiplication.
摘要翻译：双精度乘法器，用于使用2的补码单精度乘数执行两个双精度数据的乘法。 2n-1位双精度数据被分成通过取高精度数据的高n位形成的一个单精度数据，另一个单精度数据通过在剩余的n位精度数据的最高有效位之前加上“0” 1位双精度数据。用于执行双精度乘法的装置消除了识别符号位的必要性，并提高双精度倍增的速度。

36. 发明授权

US4700324A Digital circuit performing an arithmetic operation with an overflow 失效
标题翻译：数字电路用溢出进行算术运算
公开(公告)号：US4700324A
公开(公告)日：1987-10-13
申请号：US647507
申请日：1984-09-05
申请人： Kohji Doi , Yuichi Kawakami
发明人： Kohji Doi , Yuichi Kawakami
IPC分类号： G06F7/38 , G06F7/544 , G06F17/10
CPC分类号： G06F7/5443 , G06F7/4991
摘要： A digital circuit for executing an arithmetic operation includes an overflow processing capability. The overflow processing is performed by a shifter to correct a decimal point. The shifter is used to shift a result of the arithmetic operation with an overflow and to shift a data to be operated by an arithmetic unit. The result and the data are applied to the shifter via a multiplexer, and either one of them is transferred to the shifter. The shifter is controlled such that the result of the arithmetic operation is shifted by one bit, while the data is shifted according to the number of overflows. As the result, the digital circuit can perform an arithmetic operation at a high speed by means of a simple hardware element.
摘要翻译：用于执行算术运算的数字电路包括溢出处理能力。溢出处理由移位器执行以校正小数点。移位器用于以溢出方式移动算术运算的结果，并移动要由运算单元运行的数据。结果和数据通过复用器应用于移位器，并且其中的一个被传送到移位器。控制移位器，使得算术运算的结果移位一位，同时根据溢出次数移位数据。结果，数字电路可以通过简单的硬件元件高速执行算术运算。

37. 发明授权

US4379338A Arithmetic circuit with overflow detection capability 失效
标题翻译：具有溢出检测能力的算术电路
公开(公告)号：US4379338A
公开(公告)日：1983-04-05
申请号：US209250
申请日：1980-11-21
申请人： Takao Nishitani , Yuichi Kawakami
发明人： Takao Nishitani , Yuichi Kawakami
IPC分类号： G06F7/38 , G06F7/00 , G06F7/50 , G06F7/505 , G06F7/509 , G06F17/10 , G06F7/48
CPC分类号： G06F7/5095 , G06F7/4991
摘要： Overflow monitoring circuitry for an arithmetic unit offsets consecutive positive and negative overflows against one another to eliminate unnecessary overflow compensation during an arithmetic operation. In a first embodiment, an up/down counter is used to count positive overflows in one direction and negative overflows in another, with the value of the counter at the end of the arithmetic operation indicating the net overflow, if any has occurred, and the most significant bit of the counter representing the direction of any net overflow. In a second embodiment, logic circuitry offsets alternate positive and negative overflows against one another but will provide an overflow signal if either an odd number of overflows occurs or if two consecutive overflows in one direction occur during the arithmetic operation.
摘要翻译：运算单元的溢出监控电路将连续的正和负溢出相互抵消，以在算术运算期间消除不必要的溢出补偿。在第一实施例中，使用向上/向下计数器对一个方向上的正溢出进行计数，并在另一方向上计数负溢出，而在算术运算结束时的计数器的值表示净溢出（如果有的话），并且计数器的最高有效位表示任何净溢出的方向。在第二实施例中，逻辑电路相互抵消交替的正和负溢出，但是如果发生奇数个溢出或者在算术运算期间发生两个连续的一个方向溢出，则会提供溢出信号。

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