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31. 发明授权

US08940615B2 Method of forming isolation structure 有权
标题翻译：形成隔离结构的方法
公开(公告)号：US08940615B2
公开(公告)日：2015-01-27
申请号：US13607798
申请日：2012-09-09
申请人： Te-Lin Sun , Chien-Liang Lin , Yu-Ren Wang
发明人： Te-Lin Sun , Chien-Liang Lin , Yu-Ren Wang
IPC分类号： H01L21/76 , H01L21/31
CPC分类号： H01L21/76232 , H01L21/02247 , H01L21/02252 , H01L21/3211 , H01L21/76237 , H01L29/7846
摘要： The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench.
摘要翻译：本发明提供一种形成隔离结构的方法。提供衬底，并且在衬底中形成沟槽。接下来，在沟槽的表面上形成半导体层。进行氮化，以在半导体层中形成氮化层。最后，将绝缘层填充到沟槽中。

32. 发明授权

US08802579B2 Semiconductor structure and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08802579B2
公开(公告)日：2014-08-12
申请号：US13271256
申请日：2011-10-12
申请人： Chien-Liang Lin , Shao-Wei Wang , Yu-Ren Wang , Ying-Wei Yen
发明人： Chien-Liang Lin , Shao-Wei Wang , Yu-Ren Wang , Ying-Wei Yen
IPC分类号： H01L21/31 , H01L21/28 , H01L21/02 , H01L29/51 , H01L29/66 , H01L29/49
CPC分类号： H01L21/02181 , H01L21/0228 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process.
摘要翻译：半导体工艺包括以下步骤。提供基板。在基板上形成具有高介电常数的介电层，其中形成电介质层的步骤包括：（a）形成金属氧化物层; （b）对金属氧化物层进行退火处理; 并重复执行步骤（a）和（b）。另外，本发明还提供了由所述半导体工艺形成的半导体结构。

33. 发明申请

US20130280878A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20130280878A1
公开(公告)日：2013-10-24
申请号：US13451484
申请日：2012-04-19
申请人： Tsai-Yu Wen , Tsuo-Wen Lu , Yu-Ren Wang
发明人： Tsai-Yu Wen , Tsuo-Wen Lu , Yu-Ren Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/3105 , H01L29/4983 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor process includes the following steps. A gate structure is formed on a substrate. An oxide layer is formed and covers the gate structure and the substrate. A plasma process without oxygen is performed to densify the oxide layer. A material layer is formed and covers the oxide layer. The material layer and the oxide layer are etched to form a dual spacer.
摘要翻译：半导体工艺包括以下步骤。在基板上形成栅极结构。形成氧化物层并覆盖栅极结构和衬底。进行无氧的等离子体处理以致密化氧化物层。形成材料层并覆盖氧化物层。蚀刻材料层和氧化物层以形成双重间隔物。

34. 发明申请

US20130093064A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130093064A1
公开(公告)日：2013-04-18
申请号：US13271256
申请日：2011-10-12
申请人： Chien-Liang Lin , Shao-Wei Wang , Yu-Ren Wang , Ying-Wei Yen
发明人： Chien-Liang Lin , Shao-Wei Wang , Yu-Ren Wang , Ying-Wei Yen
IPC分类号： H01L29/00 , H01L21/31
CPC分类号： H01L21/02181 , H01L21/0228 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process.
摘要翻译：半导体工艺包括以下步骤。提供基板。在基板上形成具有高介电常数的介电层，其中形成电介质层的步骤包括：（a）形成金属氧化物层; （b）对金属氧化物层进行退火处理; 并重复执行步骤（a）和（b）。另外，本发明还提供了由所述半导体工艺形成的半导体结构。

35. 发明申请

US20130045594A1 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE 有权
标题翻译：具有金属栅的半导体器件的制造方法
公开(公告)号：US20130045594A1
公开(公告)日：2013-02-21
申请号：US13212187
申请日：2011-08-18
申请人： Yu-Ren Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh
发明人： Yu-Ren Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh
IPC分类号： H01L21/28
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L29/517 , H01L29/66545 , H01L29/7848
摘要： A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.
摘要翻译：具有金属栅极的半导体器件的制造方法包括提供至少形成有第一半导体器件的衬底，在第一半导体器件中形成第一栅极沟槽，在第一栅极沟槽中形成第一功函数金属层，以及对第一功函数金属层进行解耦等离子体氧化。

36. 发明申请

US20130001707A1 FABRICATING METHOD OF MOS TRANSISTOR, FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF 审中-公开
标题翻译： MOS晶体管的制造方法，Fin场效应晶体管及其制造方法
公开(公告)号：US20130001707A1
公开(公告)日：2013-01-03
申请号：US13174711
申请日：2011-06-30
申请人： Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang , Chan-Lon Yang , Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang , Chan-Lon Yang , Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L21/02332 , H01L29/512 , H01L29/66795 , H01L29/785
摘要： A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.
摘要翻译： MOS晶体管的制造方法包括以下步骤。提供基板。在基板上形成栅介电层。进行包含氮等离子体和氦气的氮化处理，以对栅介质层进行氮化。还提供了鳍状场效应晶体管及其制造方法。

37. 发明申请

US20120264284A1 MANUFACTURING METHOD FOR METAL GATE STRUCTURE 审中-公开
标题翻译：金属结构的制造方法
公开(公告)号：US20120264284A1
公开(公告)日：2012-10-18
申请号：US13086410
申请日：2011-04-14
申请人： Shao-Wei Wang , Ying-Wei Yen , Yu-Ren Wang , Chien-Liang Lin
发明人： Shao-Wei Wang , Ying-Wei Yen , Yu-Ren Wang , Chien-Liang Lin
IPC分类号： H01L21/28
CPC分类号： H01L29/66545 , H01L21/28088 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A manufacturing method for a metal gate structure includes providing a substrate having a gate trench formed thereon, forming a work function metal layer in the gate trench, and performing an annealing process to the work function metal layer. The annealing process is performed at a temperature between 400° C. and 500° C., and in a bout 20 seconds to about 180 seconds.
摘要翻译：金属栅极结构的制造方法包括提供其上形成有栅极沟槽的衬底，在栅极沟槽中形成功函数金属层，并对功函数金属层进行退火处理。退火过程在400℃和500℃之间的温度下进行，并且在20秒至约180秒的温度下进行。

38. 发明授权

US08183118B2 Method for fabricating MOS transistor 有权
标题翻译：制造MOS晶体管的方法
公开(公告)号：US08183118B2
公开(公告)日：2012-05-22
申请号：US12868739
申请日：2010-08-26
申请人： Tsuo-Wen Lu , Tsai-Fu Hsiao , Yu-Ren Wang , Shu-Yen Chan
发明人： Tsuo-Wen Lu , Tsai-Fu Hsiao , Yu-Ren Wang , Shu-Yen Chan
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/6653 , H01L29/7834
摘要： The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.
摘要翻译：本发明公开了一种制造MOS晶体管的方法。提供其上具有栅极结构的基板。氮化硅层沉积在栅极结构上。然后执行干蚀刻工艺以在栅极结构的每个侧壁上限定氮化硅间隔物，并且在栅极结构的每一侧上的源极/漏极区域中形成凹陷。沉积覆盖栅极结构和凹陷的过渡层。执行预外延清洁处理以去除过渡层。对基板进行预烘烤处理。进行外延生长工艺以在凹槽中生长嵌入的SiGe层。去除一次性氮化硅间隔物。

39. 发明授权

US07214631B2 Method of forming gate dielectric layer 有权
标题翻译：形成栅极电介质层的方法
公开(公告)号：US07214631B2
公开(公告)日：2007-05-08
申请号：US10906008
申请日：2005-01-31
申请人： Yu-Ren Wang , Ying-Wei Yen , Liyuan Cheng , Kuo-Tai Huang
发明人： Yu-Ren Wang , Ying-Wei Yen , Liyuan Cheng , Kuo-Tai Huang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/0214 , H01L21/02332 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： A method for forming a gate dielectric layer is described. A silicon oxide layer is formed on a semiconductor substrate. Then, a first and a second nitrogen doping processes are performed in sequence to the silicon oxide layer using plasma comprising inert gas and gaseous nitrogen to form a gate dielectric layer. The first nitrogen doping process is performed at a lower power, a lower pressure and a higher inert gas to nitrogen gas ratio than those at the second nitrogen doping process. The combination of the deeper nitrogen distribution of the first nitrogen doping process and the shallower nitrogen distribution of the second nitrogen doping process produces a flatter total nitrogen distribution profile so that leakage current from electron tunneling through the gate dielectric layer can be reduced.
摘要翻译：描述了形成栅介质层的方法。在半导体衬底上形成氧化硅层。然后，使用包含惰性气体和气态氮的等离子体，依次对氧化硅层进行第一和第二氮掺杂工艺以形成栅极电介质层。第一氮掺杂过程在低功率，低压和高惰性气体与氮气比之下进行，与第二氮掺杂过程相比。第一氮掺杂过程的较深氮分布和第二氮掺杂过程的较浅氮分布的组合产生更平坦的总氮分布分布，从而可以减少来自电介质穿过栅介质层的漏电流。

40. 发明授权

US08551876B2 Manufacturing method for semiconductor device having metal gate 有权
标题翻译：具有金属栅极的半导体器件的制造方法
公开(公告)号：US08551876B2
公开(公告)日：2013-10-08
申请号：US13212187
申请日：2011-08-18
申请人： Yu-Ren Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh
发明人： Yu-Ren Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh
IPC分类号： H01L21/28
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L29/517 , H01L29/66545 , H01L29/7848
摘要： A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.
摘要翻译：具有金属栅极的半导体器件的制造方法包括提供至少形成有第一半导体器件的衬底，在第一半导体器件中形成第一栅极沟槽，在第一栅极沟槽中形成第一功函数金属层，以及对第一功函数金属层进行解耦等离子体氧化。

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