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31. 发明授权

US6096655A Method for forming vias and trenches in an insulation layer for a dual-damascene multilevel interconnection structure 失效
标题翻译：用于在双镶嵌多层互连结构的绝缘层中形成通孔和沟槽的方法
公开(公告)号：US6096655A
公开(公告)日：2000-08-01
申请号：US146228
申请日：1998-09-02
申请人： Young Hoon Lee , Ying Zhang
发明人： Young Hoon Lee , Ying Zhang
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76807 , H01L2221/1026
摘要： In a dual-damascene processes for multi level interconnection a method for forming trenches and vias in the inter-insulation is accomplished without etching out the inter-insulation layer. A thick sacrificial layer is first deposited and reversed etched to form sacrificial pillars 64 forming the vias and sacrificial bridges 72 forming the trenches. The sacrificial layer can be any material (insulator, semiconductor, or metal), provided it can be easily patterned and selectively removed later over the inter insulator layer. Thereafter a low-k inter-insulation layer is deposited around the sacrificial pillars and bridges. It is these sacrificial pillars and bridges that are etched away leaving behind vias and trenches in the inter-insulation layer. An advantage of the invention is that it replaces a difficult RIE process of vias and trenches with a much easier RIE of sacrificial pillars and bridges. In the preferred embodiment, a silicon film, either amorphous or polycrystalline, is used as the sacrificial layer.
摘要翻译：在用于多电平互连的双镶嵌工艺中，在绝缘层之间完成在绝缘间形成沟槽和通孔的方法，而不会腐蚀绝缘层。首先沉积厚的牺牲层并反向蚀刻以形成形成通孔的牺牲柱64和形成沟槽的牺牲桥72。牺牲层可以是任何材料（绝缘体，半导体或金属），只要其可以容易地被图案化并且稍后在绝缘体间层上有选择地去除。此后，在牺牲柱和桥周围沉积低k绝缘层。这些牺牲柱和桥被蚀刻掉，留下绝缘层中的通孔和沟槽。本发明的一个优点是它用牺牲柱和桥梁更容易的RIE代替了通孔和沟槽的困难的RIE过程。在优选实施例中，使用无定形或多晶硅的硅膜作为牺牲层。

32. 外观设计

USD387622S Container with lips 失效
公开(公告)号：USD387622S
公开(公告)日：1997-12-16
申请号：US53951
申请日：1996-05-02
申请人： Young Hoon Lee
设计人： Young Hoon Lee

33. 发明授权

US5548270A Bit sequential type parallel comparator 失效
标题翻译：位顺序型并行比较器
公开(公告)号：US5548270A
公开(公告)日：1996-08-20
申请号：US506378
申请日：1995-07-24
申请人： Hyoung-Gon Kim , Young-Moo Kwon , Young Hoon Lee
发明人： Hyoung-Gon Kim , Young-Moo Kwon , Young Hoon Lee
IPC分类号： G06F7/06 , G06F7/544 , G06F7/02
CPC分类号： G06F7/544
摘要： An improved bit sequential type parallel comparator capable of locating a minimum value among values of `m` bits stored in `n` registers within `m` clock cycles and the location thereof by bit-sequentially receiving those values, which includes a bit sequential type parallel comparator, which includes a minimum data detection circuit for detecting a minimum data by comparing a data of `m` bits sequentially inputted from `n` registers within `m` clock cycles; a minimum data generation circuit for generating a 1's complementary value of a minimum data using the data of `n` bits obtained by the minimum data detection circuit and an enable signal inputted from an eternally connected element; a minimum location information detection circuit for detecting a location of the minimum value among the `n` register values using the data obtained by the minimum data generation circuit and the data obtained by the minimum data detection circuit and for resetting the minimum data detection circuit upon location of the minimum value using the detected minimum location information as a reset signal; and a minimum location generation circuit for locating a minimum value register location by logically operating upon information detected by the minimum location information detection circuit and for generating a minimum value register location using a 1's complement of the data generated by the minimum data generation circuit.
摘要翻译：一种改进的比特顺序型并行比较器，其能够在'm'个时钟周期内定位存储在'n'个寄存器中的'm'比特的值中的最小值，并且通过比特顺序地接收这些值来定位其位置，其包括比特序列类型并行比较器，其包括最小数据检测电路，用于通过比较在'm'个时钟周期内从'n'个寄存器顺序输入的'm'位的数据来检测最小数据; 使用由最小数据检测电路获得的“n”位的数据和从永久连接的元件输入的使能信号来生成最小数据的1的互补值的最小数据生成电路; 最小位置信息检测电路，用于使用由最小数据生成电路获得的数据和由最小数据检测电路获得的数据来检测“n”个寄存器值中的最小值的位置，并且用于将最小数据检测电路复位使用检测到的最小位置信息作为复位信号的最小值的位置; 以及最小位置生成电路，用于通过逻辑地操作由最小位置信息检测电路检测到的信息来定位最小值寄存器位置，并且使用由最小数据生成电路产生的数据的1的补码来生成最小值寄存器位置。

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