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31. 发明授权

US07752613B2 Disambiguation in dynamic binary translation 有权
标题翻译：消除动态二进制翻译
公开(公告)号：US07752613B2
公开(公告)日：2010-07-06
申请号：US11634399
申请日：2006-12-05
申请人： Bolei Guo , Youfeng Wu
发明人： Bolei Guo , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F9/45516 , G06F8/433
摘要： A method and apparatus for disambiguating in a dynamic binary translator is described. The method comprises selecting a code segment for load-store memory disambiguation based at least in part on a measure of likelihood of frequency of execution of the code segment; heuristically identifying one or more ambiguous memory dependencies in the code segment for disambiguation by runtime checks; based at least in part on inspecting instructions in the code segment, and using a pointer analysis of the code segment to identify all other ambiguous memory dependencies that can be removed by the runtime checks.
摘要翻译：描述了用于在动态二进制转换器中消除歧义的方法和装置。该方法包括至少部分地基于代码段的执行频率的可能性的度量来选择用于加载存储器消除歧义的代码段; 启发式地通过运行时检查来识别代码段中的一个或多个不明确的存储器依赖关系以消除歧义; 至少部分地基于代码段中的检查指令，并使用代码段的指针分析来识别运行时检查可以移除的所有其他模糊的存储器依赖性。

32. 发明申请

US20100083236A1 COMPACT TRACE TREES FOR DYNAMIC BINARY PARALLELIZATION 有权
标题翻译：用于动态二进制并行化的紧凑跟踪
公开(公告)号：US20100083236A1
公开(公告)日：2010-04-01
申请号：US12242371
申请日：2008-09-30
申请人： Joao Paulo Porto , Edson Borin , Youfeng Wu , Cheng Wang
发明人： Joao Paulo Porto , Edson Borin , Youfeng Wu , Cheng Wang
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： Methods and apparatus relating to compact trace trees for dynamic binary parallelization are described. In one embodiment, a compact trace tree (CTT) is generated to improve the effectiveness of dynamic binary parallelization. CTT may be used to determine which traces are to be duplicated and specialized for execution on separate processing elements. Other embodiments are also described and claimed.
摘要翻译：描述了用于动态二进制并行化的紧凑跟踪树的方法和设备。在一个实施例中，生成紧凑跟踪树（CTT）以提高动态二进制并行化的有效性。可以使用CTT来确定哪些跟踪被复制并专用于在单独的处理元件上执行。还描述和要求保护其他实施例。

33. 发明授权

US07383543B2 Management of reuse invalidation buffer for computation reuse 有权
标题翻译：管理重用无效缓冲区用于计算重用
公开(公告)号：US07383543B2
公开(公告)日：2008-06-03
申请号：US10410032
申请日：2003-04-08
申请人： Youfeng Wu
发明人： Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3834
摘要： A mechanism for maintaining reuse invalidation information includes a reuse buffer and a reuse invalidation buffer. The reuse buffer stores multiple instances of the reuse region. Each instance stored in the reuse buffer is identified by one or more versions. The reuse invalidation buffer contains multiple entries. Each entry in the reuse invalidation buffer includes one or more pairs of pointers pointing to instances and versions of instances held in the reuse buffer.
摘要翻译：用于维护重用无效信息的机制包括重用缓冲器和重用无效化缓冲器。重用缓冲区存储重用区域的多个实例。存储在重用缓冲区中的每个实例由一个或多个版本来标识。重用无效缓冲区包含多个条目。重用无效缓冲器中的每个条目包括一对或多对指向重定向缓冲区中保存的实例和版本的指针。

34. 发明申请

US20070079296A1 Compressing "warm" code in a dynamic binary translation environment 有权
标题翻译：在动态二进制翻译环境中压缩“温暖”代码
公开(公告)号：US20070079296A1
公开(公告)日：2007-04-05
申请号：US11240551
申请日：2005-09-30
申请人： Zhiyuan Li , Youfeng Wu
发明人： Zhiyuan Li , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F9/45516
摘要： Selected regions of native instructions translated in a DBT environment from non-native instructions are compressed based on the independent compression of different fields of selected instructions using compression tables to reduce a length of selected fields. The regions of compressed instructions are stored and de-compressed into the native instructions during subsequent execution using de-compression tables. Specifically, for native instructions of a selected region, selected types of opcodes and/or operands may be compressed independently. The types may be selected by profiling the opcodes using benchmark programs and creating an opcode conversion table prior to compression, and scanning of the operands and creating an operand conversion table during compression of the opcodes.
摘要翻译：基于使用压缩表的所选指令的不同字段的独立压缩来压缩来自非本地指令的DBT环境中的本地指令的所选区域被压缩以减少所选字段的长度。压缩指令的区域在后续执行期间使用解压缩表存储和解压缩为本地指令。具体地，对于所选区域的本地指令，可以独立压缩所选择的操作码类型和/或操作数。可以通过使用基准程序对操作码进行分析来选择类型，并在压缩之前创建操作码转换表，扫描操作数并在压缩操作码期间创建操作数转换表。

35. 发明申请

US20070079293A1 Two-pass MRET trace selection for dynamic optimization 有权
标题翻译：双向MRET跟踪选择用于动态优化
公开(公告)号：US20070079293A1
公开(公告)日：2007-04-05
申请号：US11241527
申请日：2005-09-30
申请人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz , Youfeng Wu
发明人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz , Youfeng Wu
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： A first potential hot trace of a program is determined. A second potential hot trace of the program is determined. A common path from the first potential hot trace and the second potential hot trace is selected as the selected hot trace of the program.
摘要翻译：确定程序的第一个潜在的热迹。确定程序的第二个潜在的热迹。选择第一个潜在热痕迹和第二个潜在热痕迹的常见路径作为程序的选定热痕迹。

36. 发明授权

US07188234B2 Run-ahead program execution with value prediction 失效
标题翻译：带有价值预测的预测程序执行
公开(公告)号：US07188234B2
公开(公告)日：2007-03-06
申请号：US10017793
申请日：2001-12-12
申请人： Youfeng Wu , Tin-Fook Ngai
发明人： Youfeng Wu , Tin-Fook Ngai
IPC分类号： G06F9/312
CPC分类号： G06F9/383 , G06F9/3832 , G06F9/3842 , G06F9/3861
摘要： A data processing apparatus, a computer, an article including a machine-accessible medium, and a method of processing data are disclosed. The data processing apparatus may include a pair of pipelines sharing an instruction cache, data cache, and a branch predictor with the second pipeline running ahead of the first pipeline using a data value prediction module. The pipelines may be included in one or more processors and coupled to a memory to form a computer. The method includes executing a plurality of instructions using the pipeline pair, such that when a cache miss is encountered by the second pipeline during execution of a LOAD instruction, the data value prediction module supplies a predicted load value in lieu of a cached value, enabling continued execution of the plurality of instructions by the second pipeline without waiting for the return of the cached value.
摘要翻译：公开了一种数据处理装置，计算机，包括机器可访问介质的物品和处理数据的方法。数据处理装置可以包括使用数据值预测模块，共享指令高速缓存，数据高速缓存和分支预测器的一对管线，其中第二管线在第一管线之前运行。管线可以包括在一个或多个处理器中并且耦合到存储器以形成计算机。该方法包括使用流水线对来执行多个指令，使得当在执行LOAD指令期间由第二流水线遇到高速缓存未命中时，数据值预测模块提供代替缓存值的预测负载值，使能通过第二管道继续执行多个指令，而不等待返回缓存的值。

37. 发明授权

US07120749B2 Cache mechanism 失效
标题翻译：缓存机制
公开(公告)号：US07120749B2
公开(公告)日：2006-10-10
申请号：US10803452
申请日：2004-03-18
申请人： Ryan Rakvic , Youfeng Wu , Bryan Black , John Shen
发明人： Ryan Rakvic , Youfeng Wu , Bryan Black , John Shen
IPC分类号： G06F12/12
CPC分类号： G06F12/0848 , G06F12/0888
摘要： According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital loads to be processed at the CPU, and a third cache memory coupled to the CPU, the first cache memory and the second cache memory to store non-vital loads to be processed at the CPU.
摘要翻译：根据一个实施例，公开了一种系统。该系统包括中央处理单元（CPU），第一高速缓存存储器，其耦合到CPU以仅存储要在CPU处理的重要负载的数据;耦合到CPU的第二高速缓存存储器，在CPU处理的重要负载，以及耦合到CPU，第一高速缓冲存储器和第二高速缓冲存储器的第三高速缓存存储器，用于存储要在CPU处理的非重要负载。

38. 发明授权

US07100155B1 Software set-value profiling and code reuse 有权
标题翻译：软件设置值分析和代码重用
公开(公告)号：US07100155B1
公开(公告)日：2006-08-29
申请号：US09522510
申请日：2000-03-10
申请人： Youfeng Wu
发明人： Youfeng Wu
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/443
摘要： An apparatus and method for profiling candidate reuse regions and candidate load instructions aids in the selection of computation reuse regions and computation reuse instructions with good reuse qualities. Registers holding input values for candidate reuse regions are sampled periodically when the candidate reuse region is encountered. The register contents are combined into set-values. When a relatively small number of set-values account for a large percentage of occurrences, the candidate reuse region may be a good computation reuse region. Load instructions are profiled for the location accessed and the value loaded. The location and value are combined into location-values. The relative occurrence frequency of location-values can be used to evaluate load instructions as candidate instructions for reuse.
摘要翻译：用于分析候选重用区域和候选加载指令的装置和方法有助于选择具有良好重用质量的计算重用区域和计算重用指令。当候选重用区域被遇到时，周期性地对候选重用区域保持输入值的寄存器进行采样。寄存器内容被组合成设定值。当相对较少数量的设定值占很大比例时，候选重用区域可能是一个很好的计算重用区域。为访问的位置和加载的值分配加载指令。位置和值被组合成位置值。位置值的相对出现频率可用于评估加载指令作为重用的候选指令。

39. 发明授权

US06571385B1 Early exit transformations for software pipelining 有权
标题翻译：软件流水线的早期退出转换
公开(公告)号：US06571385B1
公开(公告)日：2003-05-27
申请号：US09273947
申请日：1999-03-22
申请人： Kalyan Muthukumar , Dong-Yuan Chen , Youfeng Wu , Daniel M. Lavery
发明人： Kalyan Muthukumar , Dong-Yuan Chen , Youfeng Wu , Daniel M. Lavery
IPC分类号： G06F944
CPC分类号： G06F9/325 , G06F8/4452 , G06F9/30072 , G06F9/30094
摘要： The invention is directed to the transformation of software loops having early exit conditions, thereby allowing the loops to be more effectively converted to a single basic block for software pipelining. The invention assigns a predicate register for each early exit condition of the software loop. The predicate registers are set when the corresponding early exit condition is satisfied. In this manner, when the loop terminates the predicate registers can be examined to indicate which early exit conditions were satisfied. The invention produces loops having a lower recurrence II and resource II than conventional techniques.
摘要翻译：本发明涉及具有早期退出条件的软件循环的变换，从而允许循环更有效地转换成用于软件流水线化的单个基本块。本发明为软件循环的每个提前退出条件分配谓词寄存器。当满足相应的提前退出条件时，设定谓词寄存器。以这种方式，当循环终止时，可以检查谓词寄存器以指示哪个早期退出条件被满足。本发明产生具有比常规技术更低的复发II和资源II的环。

40. 发明授权

US5655122A Optimizing compiler with static prediction of branch probability, branch frequency and function frequency 失效
标题翻译：优化编译器与分支概率，分支频率和功能频率的静态预测
公开(公告)号：US5655122A
公开(公告)日：1997-08-05
申请号：US417219
申请日：1995-04-05
申请人： Youfeng Wu
发明人： Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F8/445 , G06F8/4441
摘要： A compiler and method for optimizing a program based on branch probabilities, branch frequencies and function frequencies. A number of algorithms executed by the compiler determine statically from the program code the probabilities that branches with the program are taken and how often the branches are taken. With this information, the compiler arranges the object code in memory to improve execution of the program. The frequency of functions within the code may be determined from the branch probability and branch frequency information. The compiler uses the function frequency information to arrange the functions in a desirable order, such as storing function pairs with the highest global call frequencies on the same memory page. This minimizes the number of calls to functions that are stored on disk and thus improves the speed of execution of the program.
摘要翻译：一种基于分支概率，分支频率和功能频率优化程序的编译器和方法。由编译器执行的许多算法从程序代码中静态地确定采用程序分支的概率以及分支采用的频率。使用这些信息，编译器将目标代码安排在内存中，以改善程序的执行。代码内的功能频率可以根据分支概率和分支频率信息来确定。编译器使用功能频率信息以期望的顺序排列功能，例如在同一存储器页面上存储具有最高全局呼叫频率的功能对。这最小化了对存储在磁盘上的函数的调用次数，从而提高了程序的执行速度。

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