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31. 发明授权

US5463581A Memory in which improvement is made as regards a precharge operation of data readout routes 失效
标题翻译：关于数据读出路径的预充电操作进行改进的存储器
公开(公告)号：US5463581A
公开(公告)日：1995-10-31
申请号：US295076
申请日：1994-08-26
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C7/1048
摘要： In a semiconductor memory device having first and second main data amplifiers (27, 28) for electrically charging a plurality of read bus pairs (23, 24), a precharge control circuit (26) controls operation of first and second main data amplifiers so that selected ones of the read bus pairs are electrically charged during a predetermined burst period except when each of the first and the second main data amplifiers produces a difference signal. When each of the read bus pairs has a read bus potential difference, each of the first and the second main data amplifiers produces the difference signal and electrically charges each of the read bus pairs in accordance with the difference signal. The read bus potential difference is produced dependent on a bit line potential difference which is produced in each of bit line pairs.
摘要翻译：在具有用于对多个读总线对（23,24）进行充电的第一和第二主数据放大器（27,28）的半导体存储器件中，预充电控制电路（26）控制第一和第二主数据放大器的操作，使得所选择的读总线对在预定的突发周期期间被充电，除了当第一和第二主数据放大器中的每一个产生差分信号时。当每个读总线对具有读总线电位差时，第一和第二主数据放大器中的每一个产生差信号，并根据该差信号对每个读总线对进行电荷充电。读总线电位差取决于每个位线对中产生的位线电位差产生。

32. 发明授权

US08015457B2 Redundancy circuit and semiconductor memory device 有权
标题翻译：冗余电路和半导体存储器件
公开(公告)号：US08015457B2
公开(公告)日：2011-09-06
申请号：US12000373
申请日：2007-12-12
申请人： Yasuji Koshikawa , Yousuke Kawamata
发明人： Yasuji Koshikawa , Yousuke Kawamata
IPC分类号： G11C29/44 , G11C29/50
CPC分类号： G11C17/14 , G11C29/02 , G11C29/027 , G11C29/835
摘要： Disclosed is a circuit for deciding whether or not a plural number of redundancy ROM circuits have been programmed in a preset order, with regards to addresses. In at least one of first to n-th redundancy memory circuits, an address to be substituted by a redundant address is recorded and a redundancy selection signal is output when an access address is coincident with the programmed address. It is presupposed that repair addresses are programmed from the first to the n-th redundancy ROM circuits in an ascending order with regards to address. If it is detected under this condition that a redundancy selection signal has been output from the i+1'st redundancy memory circuit while no redundancy selection signal is being output from the i-th redundancy memory circuit, an SR flip-flop is set and the sequence of the substitution decision outputs is decided to be a reversed sequence.
摘要翻译：公开了一种用于判定多个冗余ROM电路是否已经以预设顺序对地址进行编程的电路。在第一至第n冗余存储器电路中的至少一个中，记录要由冗余地址替代的地址，并且当访问地址与编程的地址一致时，输出冗余选择信号。假设修复地址从第一到第n冗余ROM电路以关于地址的升序被编程。如果在该条件下检测到从第i + 1'冗余存储电路输出了冗余选择信号，而没有从第i冗余存储电路输出冗余选择信号，则设置SR触发器，替代决策输出的顺序被确定为逆序列。

33. 发明授权

US07835213B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07835213B2
公开(公告)日：2010-11-16
申请号：US12325026
申请日：2008-11-28
申请人： Chiaki Dono , Yasuji Koshikawa
发明人： Chiaki Dono , Yasuji Koshikawa
IPC分类号： G11C5/14
CPC分类号： G11C7/1051 , G11C7/1057 , G11C11/404 , G11C11/407 , H01L21/823462 , H01L27/105 , H01L27/10873 , H01L27/10897
摘要： A semiconductor memory device with low power consumption and improved transfer rate of an input/output buffer at reduced manufacturing cost is provided. Thick-film transistors are used for a memory cell array 33, a row decoder 30, and a sense amplifier 32, surrounded by a bold broken line. Thick-film transistors having a threshold voltage lower than the aforementioned transistors are used for input buffers 11 to 13 and an input/output buffer 26, surrounded by a bold line. Thin-film transistors are used for a clock generator 16, a command decoder 17, a mode register 18, a controller 20, a row address buffer and refresh counter 21, a column address buffer and burst counter 22, a data control circuit 23, a latch circuit 24, a DLL 25, and a column decoder 31.
摘要翻译：提供了一种半导体存储器件，其以降低的制造成本具有低功耗和改善的输入/输出缓冲器的传送速率。厚膜晶体管用于由粗体虚线包围的存储单元阵列33，行解码器30和读出放大器32。具有低于上述晶体管的阈值电压的厚膜晶体管用于由粗线包围的输入缓冲器11至13和输入/输出缓冲器26。薄膜晶体管用于时钟发生器16，命令解码器17，模式寄存器18，控制器20，行地址缓冲器和刷新计数器21，列地址缓冲器和突发计数器22，数据控制电路23，锁存电路24，DLL 25和列解码器31。

34. 发明授权

US07417908B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07417908B2
公开(公告)日：2008-08-26
申请号：US10564626
申请日：2004-07-13
申请人： Sumio Ogawa , Yasuji Koshikawa
发明人： Sumio Ogawa , Yasuji Koshikawa
IPC分类号： G11C7/00
CPC分类号： G11C29/808
摘要： In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired.The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.
摘要翻译：在设置有用于对缺陷存储单元进行修复的冗余电路的半导体存储器件中，可以有效地修复不均匀分布的存储单元缺陷。半导体存储器件具有多个存储块，并且存储块包括多个段。代替段的缺陷数据的冗余存储块物理地提供给多个存储块中的每一个。冗余存储器块的块地址被共同地逻辑地分配给多个存储器块。

35. 发明授权

US07075852B2 Semiconductor memory device of hierarchy word type and sub word driver circuit 有权
标题翻译：层级字类型和子字驱动电路半导体存储器件
公开(公告)号：US07075852B2
公开(公告)日：2006-07-11
申请号：US10972486
申请日：2004-10-26
申请人： Chiaki Dono , Yasuji Koshikawa
发明人： Chiaki Dono , Yasuji Koshikawa
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C8/08
摘要： In a sub word driver circuit in a semiconductor memory device of a hierarchy word structure using a main word line signal and a sub word line signal, a first NMOS transistor and a first PMOS transistor are connected in series. A second NMOS transistor is connected with a node between the first PMOS transistor and the first NMOS transistor. The source of the first PMOS transistor is connected with a sub word line inverted signal obtained by inverting the sub word line signal, and the source of the first NMOS transistor is connected with a first negative voltage. A single main word line signal is connected to a gate of the first PMOS transistor and a gate of the first NMOS transistor, and the sub word line signal is connected with a gate of the second NMOS transistor.
摘要翻译：在使用主字线信号和子字线信号的分层字结构的半导体存储器件中的子字驱动器电路中，串联连接第一NMOS晶体管和第一PMOS晶体管。第二NMOS晶体管与第一PMOS晶体管和第一NMOS晶体管之间的节点连接。第一PMOS晶体管的源极与通过反相子字线信号而获得的副字线反相信号连接，第一NMOS晶体管的源极与第一负电压连接。单个主字线信号连接到第一PMOS晶体管的栅极和第一NMOS晶体管的栅极，并且子字线信号与第二NMOS晶体管的栅极连接。

36. 发明授权

US06452844B2 Semiconductor storage device having redundancy circuit for replacement of defect cells under tests 有权
标题翻译：具有冗余电路的半导体存储装置，用于更换被测试的缺陷单元
公开(公告)号：US06452844B2
公开(公告)日：2002-09-17
申请号：US09739490
申请日：2000-12-18
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C700
CPC分类号： G11C29/72 , G11C29/40
摘要： A semiconductor storage device such as a DRAM is configured to enable testing on defectiveness of memory cells by an existing memory tester, which locates defect cells to be replaced with redundancy cells by a redundancy circuit. Herein, a write circuit writes multiple-bit data to memory cells of a memory cell array under testing. Then, the multiple-bit data are read from the memory cell array by a read circuit and are compared with original one to make decisions of “pass” or “fail” on the memory cells by the memory tester. Specifically, the read circuit is configured by plural pairs of a data output circuit and a data compression circuit with respect to plural sets of prescribed data each of which consists of a prescribed number of bits corresponding to prescribed memory cells which are subjected to simultaneous replacement. The data compression circuit is configured by an exclusive-or circuit that compresses a certain type of the prescribed data to specific data having a specific logical value. Or, the data compression circuit is configured using two exclusive-or circuits that compress different types of the prescribed data to specific data. The specific data is forwarded as single-bit data, based on which the memory tester makes decisions of “pass” or “fail” on the memory cells corresponding to bits of the prescribed data being read out.
摘要翻译：诸如DRAM的半导体存储装置被配置为能够通过现有存储器测试器对存储器单元的缺陷进行测试，该存储器测试器通过冗余电路定位要被冗余单元替换的缺陷单元。这里，写入电路将多位数据写入被测试的存储单元阵列的存储单元。然后，通过读取电路从存储单元阵列中读取多位数据，并将其与原始数据进行比较，以通过存储器测试器对存储器单元进行“通过”或“失败”判定。具体地，读取电路由多对数据输出电路和数据压缩电路构成，该数据输出电路和数据压缩电路相对于多组规定数据构成，每组规定数据由对应于同时替换的规定存储器单元的规定数量的位组成。数据压缩电路由将特定类型的规定数据压缩到具有特定逻辑值的特定数据的异或电路配置。或者，数据压缩电路使用将不同类型的规定数据压缩到特定数据的两个专用或电路来配置。特定数据作为单位数据转发，基于此，存储器测试器对与读出的规定数据的位对应的存储单元进行“通过”或“失败”判定。

37. 发明授权

US06414887B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06414887B2
公开(公告)日：2002-07-02
申请号：US09846252
申请日：2001-05-02
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C700
CPC分类号： G11C29/84
摘要： A semiconductor memory device is designed to speed up the selection of a word line. The semiconductor memory device comprises a plurality of normal row decoders for decoding input row address data for specifying word lines when access is made to those of memory cells of a memory cell array which are other than a redundant row of memory cells, thereby selecting those word lines to which those memory cells that are other than the redundant row of memory cells are connected; a redundant row decoder for specifying that word line to which the redundant row of memory cells is connected when access is made to any memory cell which belongs to the redundant row; decision means for determining whether or not to select a memory cell belonging to the redundant row based on the input row address data and selecting the redundant row decoder when selecting the memory cell belonging to the redundant row; and control means for changing only those word lines which are connected to the normal row decoders from an active state to a standby state based on a decision output of the decision means when the decision means has determined to select a memory cell belonging to the redundant row when changing the word lines connected to the normal row decoders from a standby state to an active state.
摘要翻译：半导体存储器件被设计成加速字线的选择。半导体存储器件包括多个正常行解码器，用于当对与存储器单元的冗余行不同的存储单元阵列的存储单元进行访问时，用于解码用于指定字线的输入行地址数据，从而选择这些字与存储器单元的冗余行不同的那些存储单元被连接到的行; 冗余行解码器，用于当对属于所述冗余行的任何存储单元进行访问时，指定所述冗余行存储单元连接到的字线; 决定装置，用于基于所输入的行地址数据确定是否选择属于所述冗余行的存储单元，并且在选择属于所述冗余行的存储单元时选择所述冗余行解码器; 以及控制装置，用于当判定装置确定选择属于冗余行的存储单元时，根据判定装置的判定输出，仅将那些连接到正常行解码器的字线从活动状态改变为待机状态当将连接到正常行解码器的字线从待机状态改变为活动状态时。

38. 发明授权

US06385104B2 Semiconductor memory device having a test mode decision circuit 有权
标题翻译：具有测试模式决定电路的半导体存储器件
公开(公告)号：US06385104B2
公开(公告)日：2002-05-07
申请号：US09839504
申请日：2001-04-20
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C700
CPC分类号： G11C29/50
摘要： The semiconductor memory device according to the present invention comprises a memory cell array having a plurality of memory cells, a plurality of bit lines, a plurality of word lines, a row decoder which selects a prescribed word line in response to a row address and a control signal, a test mode decision circuit which generates a test signal by deciding that the device is in a test mode, a control signal generating circuit which brings the control signal to the activated state and keeps it there for a prescribed duration in response to an instruction signal, wherein the control signal generating circuit has a means for setting the change of the control signal to the inactivated state in response to the occurrence of the test signal sooner than in the normal operation.
摘要翻译：根据本发明的半导体存储器件包括具有多个存储单元的存储单元阵列，多个位线，多个字线，行解码器，其响应于行地址选择规定的字线，以及控制信号，通过判定设备处于测试模式来产生测试信号的测试模式判定电路，控制信号产生电路，其使控制信号处于激活状态，并响应于控制信号将其保持在规定的持续时间指令信号，其中所述控制信号发生电路具有用于响应于所述测试信号的发生比在所述正常操作中更早地将所述控制信号的改变设置为所述非激活状态的装置。

39. 发明授权

US06385095B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06385095B2
公开(公告)日：2002-05-07
申请号：US09729541
申请日：2000-12-04
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C1604
CPC分类号： G11C7/1093 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C11/4093 , G11C11/4096
摘要： A semiconductor memory device is provided in which no delay in writing of data occurs due to increases in the output load of the data input circuit, and which is also compatible with various bit configurations. The device comprises a plurality of data input circuits for inputting data from an external source, and a plurality of data write circuits for writing data input from the plurality of data input circuits to a memory cell array. The data to be stored is input from an external source by selectively using the plurality of data input circuits, and then each bit to be stored is distributed to the plurality of data write circuits according to the bit configuration of the data. Of the plurality of data input circuits, data input from a specific data input circuit is distributed to one of the plurality of data write circuits via another data input circuit.
摘要翻译：提供一种半导体存储器件，其中由于数据输入电路的输出负载的增加而不会导致数据写入延迟，并且其也与各种位配置兼容。该装置包括用于从外部源输入数据的多个数据输入电路和用于将从多个数据输入电路输入的数据写入存储单元阵列的多个数据写入电路。要存储的数据通过选择性地使用多个数据输入电路从外部源输入，然后根据数据的位配置将要存储的每个位分配给多个数据写入电路。在多个数据输入电路中，从特定数据输入电路输入的数据经由另一数据输入电路分配给多个数据写入电路中的一个。

40. 发明授权

US06353573B1 Clock synchronization semiconductor memory device 失效
标题翻译：时钟同步半导体存储器件
公开(公告)号：US06353573B1
公开(公告)日：2002-03-05
申请号：US09568348
申请日：2000-05-10
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C7/1072 , G11C7/1078 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4094
摘要： A clock synchronization semiconductor memory device in which the pre-charging time tRP can be accelerated by the variable delay time for write recovery. There is provided a unit for checking whether or not at least one clock cycle before the inputting of the pre-charge command is that for the write operation, and for holding the checked result. There is also provided a unit for performing switching control at the time of inputting the pre-charge command, responsive to the checked result, as to whether or not a pre-set delay time is to be introduced as from the time of inputting the pre-charge command until word line resetting.
摘要翻译：一种时钟同步半导体存储器件，其中可以通过用于写入恢复的可变延迟时间加速预充电时间tRP。提供了一个单元，用于检查在预充电命令的输入之前至少一个时钟周期是否是用于写入操作的单元，并且用于保持所检查的结果。还提供了一种用于在输入预充电命令时执行切换控制的单元，响应于检查结果，从输入预先设定的时间起是否要引入预设延迟时间充电命令直到字线复位。

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