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31. 发明授权

US4592020A Semiconductor memory device having clamp circuits 失效
标题翻译：具有钳位电路的半导体存储器件
公开(公告)号：US4592020A
公开(公告)日：1986-05-27
申请号：US554338
申请日：1983-11-22
申请人： Yoshihiro Takemae , Tomio Nakano , Kimiaki Sato
发明人： Yoshihiro Takemae , Tomio Nakano , Kimiaki Sato
IPC分类号： G11C11/413 , G11C8/08 , G11C11/407 , G11C11/40
CPC分类号： G11C8/08
摘要： A semiconductor memory device having clamp circuits, each of which operates reliably without being affected by the resistance of a word line. Each of the clamp circuits is connected to a corresponding word line and clamps the potential of the word line to a reference potential when it is in a non-selected condition. Each of the clamp circuits includes a flip-flop having a first terminal connected to the corresponding word line and a second terminal which receives a control signal for operating each of the clamp circuits. The control signal is applied to the second terminal when the potential of a selected word line exceeds at least the potential necessary for inverting the condition of the flip-flop.
摘要翻译：一种具有钳位电路的半导体存储器件，每个钳位电路可靠地操作而不受字线电阻的影响。每个钳位电路连接到相应的字线，并且当它处于非选择状态时将字线的电位钳位到参考电位。每个钳位电路包括具有连接到对应字线的第一端子的触发器和接收用于操作每个钳位电路的控制信号的第二端子。当所选字线的电位至少超过翻转触发器状态所需的电位时，将控制信号施加到第二端。

32. 发明授权

US4581720A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4581720A
公开(公告)日：1986-04-08
申请号：US535836
申请日：1983-09-26
申请人： Yoshihiro Takemae , Tomio Nakano , Kimiaki Sato
发明人： Yoshihiro Takemae , Tomio Nakano , Kimiaki Sato
IPC分类号： G11C11/401 , G11C11/406 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096 , G11C11/406 , G11C11/4087
摘要： A dynamic memory having single element storage cells. A plurality of gate circuits are connected to the column lines of the storage cell array at both ends of the column line. A plurality of sense amplifiers are disposed along both ends of the column lines and connected to the gate circuits. In accordance with switching of the gate circuits, a portion of the sense amplifiers are coupled with a portion of the column lines to perform a refresh operation and read or write operations for the storage cells connected thereto. Also, the remaining sense amplifiers are coupled with the remaining column lines to perform only the refresh operation of the storage cells connected to the remaining column lines.
摘要翻译：具有单个元件存储单元的动态存储器。在列线的两端将多个门电路连接到存储单元阵列的列线。多个读出放大器沿列线的两端设置并连接到栅极电路。根据门电路的切换，读出放大器的一部分与列线的一部分耦合，以对与其连接的存储单元执行刷新操作和读或写操作。此外，剩余的读出放大器与剩余的列线耦合，以仅执行连接到其余列线的存储单元的刷新操作。

33. 发明授权

US4379342A Semiconductor dynamic memory device 失效
标题翻译：半导体动态存储器件
公开(公告)号：US4379342A
公开(公告)日：1983-04-05
申请号：US249718
申请日：1981-03-31
申请人： Tomio Nakano , Yoshihiro Takemae
发明人： Tomio Nakano , Yoshihiro Takemae
IPC分类号： G11C11/41 , G11C5/02 , G11C7/06 , G11C8/12 , G11C11/00 , G11C11/401 , G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/40
CPC分类号： G11C11/005 , G11C11/404 , G11C11/4091 , G11C11/4096 , G11C5/025 , G11C7/065 , G11C8/12
摘要： A dynamic semiconductor memory device comprising a plurality of memory blocks each including a sense amplifier array and a pair of memory cell groups, a row decoder for selecting a row line within the plurality of memory blocks, a column decoder which is common to the plurality of memory blocks and which selectively connects a sense amplifier in each of the memory blocks to a corresponding one of the pairs of bus lines. The device also includes row block decoders which selectively enable the sense amplifier array of one of the memory blocks according to block selecting address signals, and block bus line decoders which selectively connect the pair of bus lines of each of the memory blocks to a pair of data buses according to the block selecting address signals.
摘要翻译：一种动态半导体存储器件，包括多个存储块，每个存储块包括读出放大器阵列和一对存储单元组，用于选择多个存储块内的行线的行解码器，存储器块，并且其选择性地将每个存储器块中的读出放大器连接到所述一对总线线路中的对应的一个。该装置还包括行块解码器，其根据块选择地址信号选择性地使得一个存储器块的读出放大器阵列，以及块总线解码器，其将每个存储器块的一对总线线选择性地连接到一对数据总线根据块选择地址信号。

34. 发明授权

US4158241A Semiconductor memory device with a plurality of memory cells and a sense amplifier circuit thereof 失效
标题翻译：具有多个存储单元的半导体存储器件及其读出放大器电路
公开(公告)号：US4158241A
公开(公告)日：1979-06-12
申请号：US915864
申请日：1978-06-15
申请人： Yoshihiro Takemae , Tomio Nakano
发明人： Yoshihiro Takemae , Tomio Nakano
IPC分类号： G11C11/404 , G11C11/4091 , H01L27/108 , G11C7/06
CPC分类号： G11C11/404 , G11C11/4091 , H01L27/108
摘要： A driving circuit is provided for driving a sense amplifier, especially in a semiconductor memory device of one transistor cell type. The driving circuit is comprised of MIS transistors of which gates are connected in common via at least one resistor and which have different current amplification factors. A driving signal is directly applied to the MIS transistor having lower current amplification factor in the MIS transistors and it is then applied to the MIS transistor having higher current amplification factor in the MIS transistors through the resistor with time delay for establishing a gradually increasing current from the sense amplifier to the ground to ensure the correct sensing of information stored in the memory cell.
摘要翻译：提供驱动电路用于驱动读出放大器，特别是在一个晶体管单元类型的半导体存储器件中。驱动电路由其中栅极通过至少一个电阻器共同连接并且具有不同电流放大因子的MIS晶体管组成。将驱动信号直接施加到MIS晶体管中具有较低电流放大系数的MIS晶体管，然后通过电阻器在MIS晶体管中施加具有较高电流放大系数的MIS晶体管，具有时间延迟，用于建立逐渐增加的电流将感测放大器接地，以确保存储在存储单元中的信息的正确感测。

35. 发明授权

US06498524B1 Input/output data synchronizing device 有权
标题翻译：输入/输出数据同步装置
公开(公告)号：US06498524B1
公开(公告)日：2002-12-24
申请号：US09706731
申请日：2000-11-07
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： H03L708
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

36. 发明授权

US06298004B1 Semiconductor device, semiconductor system, and digital delay circuit 失效
标题翻译：半导体器件，半导体系统和数字延迟电路
公开(公告)号：US06298004B1
公开(公告)日：2001-10-02
申请号：US08892790
申请日：1997-07-15
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： G11C800
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

37. 发明授权

US4740926A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4740926A
公开(公告)日：1988-04-26
申请号：US843356
申请日：1986-03-24
申请人： Yoshihiro Takemae , Masao Nakano , Kimiaki Sato , Nobumi Kodama
发明人： Yoshihiro Takemae , Masao Nakano , Kimiaki Sato , Nobumi Kodama
IPC分类号： G11C11/409 , G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094 , G11C11/4091
摘要： A semiconductor memory device comprises a memory cell array, a bit line charge-up circuit coupled to one of a plurality of pairs of bit lines from the memory cell array for initially charging up the one pair of bit lines to a first voltage which is lower than a power source voltage used to drive the semiconductor memory device, an active restore circuit coupled to the one pair of bit lines and a switching circuit coupled to the one pair of bit lines for disconnecting the one pair of bit lines into a first pair of bit line sections on the side of the memory cell array and a second pair of bit line sections on the side of the active restore circuit after the one pair of bit lines are initially charged up to the first voltage. The active restore circuit charges up one of the pair of bit line sections on the side of the active restore circuit to a second voltage which is higher than the first voltage depending on a datum read out from the memory cell array.
摘要翻译：半导体存储器件包括存储单元阵列，位线充电电路，其耦合到存储单元阵列的多对位线中的一对，用于将一对位线初始充电至较低的第一电压比用于驱动半导体存储器件的电源电压，耦合到一对位线的有效恢复电路和耦合到该一对位线的开关电路，用于将一对位线断开为第一对位在存储单元阵列一侧的位线部分和在一对位线开始被充电至第一电压之后的有效恢复电路侧的第二对位线部分。有源恢复电路根据从存储单元阵列读出的数据，将有源恢复电路一侧的一对位线部分中的一个充电到高于第一电压的第二电压。

38. 发明授权

US4267464A Decoder circuit 失效
标题翻译：解码电路
公开(公告)号：US4267464A
公开(公告)日：1981-05-12
申请号：US968990
申请日：1978-12-13
申请人： Yoshihiro Takemae , Masao Nakano
发明人： Yoshihiro Takemae , Masao Nakano
IPC分类号： G11C11/41 , G11C11/413 , H03K5/02 , H03K19/096 , H03K19/017 , G11C8/00
CPC分类号： H03K5/023 , H03K19/096
摘要： A decoder circuit including: a charge-up transistor for maintaining the content of an input address signal; a power supply switching transistor for controlling a charge-up current which is supplied to the charge-up transistor; a predetermined number of selection transistors which are connected at a connection point between the charge-up transistor and the power supply switching transistor so as to select an output word line, and; a bootstrap transistor which is connected to an opposite side of the connection point with respect to the charge-up transistor. The present invention enables the driving of the charge-up transistor with clock pulses having a potential level higher than the power supply line voltage V.sub.DD. The present invention also enables the driving of the power supply switching transistor by clock pulses having a potential level higher than V.sub.DD +V.sub.th wherein V.sub.+h equals the threshold voltage of the power supply switching transistor.
摘要翻译：一种解码器电路，包括：用于维持输入地址信号的内容的充电晶体管; 用于控制提供给所述充电晶体管的充电电流的电源开关晶体管; 预定数量的选择晶体管，其连接在充电晶体管和电源开关晶体管之间的连接点，以选择输出字线; 自举晶体管，其连接到相对于充电晶体管的连接点的相对侧。本发明使得能够利用具有高于电源线电压VDD的电位电平的时钟脉冲驱动充电晶体管。本发明还能够通过具有高于VDD + Vth的电位电平的时钟脉冲来驱动电源开关晶体管，其中V + h等于电源开关晶体管的阈值电压。

39. 发明授权

US6078514A Semiconductor device and semiconductor system for high-speed data transfer 失效
标题翻译：半导体器件和半导体系统，用于高速数据传输
公开(公告)号：US6078514A
公开(公告)日：2000-06-20
申请号：US61023
申请日：1998-04-16
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C11/401 , H01L21/60 , H01L25/00 , H01L27/10 , H01L25/04 , H01L23/36
CPC分类号： H01L23/60 , G11C7/1006 , G11C7/22 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L24/48 , H01L27/0266 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/1305 , H01L2924/13091 , H01L2924/30105
摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.
摘要翻译：半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是沿着至少一个存储器芯片的一侧布置。

40. 发明申请

US20050242864A1 Semiconductor device, semiconductor system, and digital delay circuit 审中-公开
标题翻译：半导体器件，半导体系统和数字延迟电路
公开(公告)号：US20050242864A1
公开(公告)日：2005-11-03
申请号：US11055784
申请日：2005-02-11
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： G06F13/42 , G11C7/10 , G11C7/22 , H03H11/26 , H03K5/00 , H03K5/13 , H03L7/081
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

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