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31. 发明授权

US07266153B2 Method and apparatus for modulating and demodulating data into a variable length code and a providing medium for implementing the method 失效
标题翻译：用于将数据调制和解调成可变长度码的方法和装置以及用于实现该方法的提供媒体
公开(公告)号：US07266153B2
公开(公告)日：2007-09-04
申请号：US11248464
申请日：2005-10-12
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H04B14/04
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.
摘要翻译： SYNC位插入部分14在添加最小运行之后将同步信号添加到一串代码，所述同步信号具有中断最大运行的模式。从而可以提供可靠的同步信号模式。

32. 发明授权

US07200175B2 Data-modulating apparatus, data-modulating method, data-demodulating apparatus, data-demodulating method, and data-providing medium 有权
标题翻译：数据调制装置，数据调制方式，数据解调装置，数据解调方式以及数据提供媒体
公开(公告)号：US07200175B2
公开(公告)日：2007-04-03
申请号：US11336061
申请日：2006-01-20
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H04B14/04
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A method and apparatus for modulating data modulates data having a length of m-bits to a variable length code having a basic code length of n-bits. A SYNC bit inserting section adds a sync signal to a train of codes, after a minimum run. The sync signal has a pattern that breaks a maximum run.
摘要翻译：用于调制数据的方法和装置将具有m比特长度的数据调制为具有n比特的基本码长度的可变长度码。 SYNC位插入部分在最小运行后将同步信号添加到代码列。同步信号具有中断最大运行的模式。

33. 发明申请

US20060115006A1 Data-modulating apparatus, data-modulating method, data-demodulating apparatus, data-demodulating method, and data-providing medium 有权
标题翻译：数据调制装置，数据调制方式，数据解调装置，数据解调方式以及数据提供媒体
公开(公告)号：US20060115006A1
公开(公告)日：2006-06-01
申请号：US11336061
申请日：2006-01-20
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H04B14/04
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.
摘要翻译： SYNC位插入部分14在添加最小运行之后将同步信号添加到一串代码，所述同步信号具有中断最大运行的模式。从而可以提供可靠的同步信号模式。

34. 发明授权

US07054373B2 Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes 有权
标题翻译：用于将数据调制和解调为可变长度代码并向代码串提供同步信号的方法和装置
公开(公告)号：US07054373B2
公开(公告)日：2006-05-30
申请号：US11088350
申请日：2005-03-24
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H04B14/04
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A data-demodulating method for demodulating a variable-length code (d, k; m, n; r) having a basic code length of n bits to data having a basic data length of m bits. A train of codes is received, and a sync signal having a pattern that breaks a maximum run is detected. The pattern is repeated twice continuously and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in a termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.
摘要翻译：一种数据解调方法，用于将具有n位基本码长的可变长度码（d，k; m，n; r）解调为具有m位基本数据长度的数据。接收一串代码，并且检测到具有中断最大运行的模式的同步信号。该模式连续重复两次，最小运行重复不超过六次。当紧接在同步信号之前的调制码序列包括在终止表中时，同步信号的第一位为“1”，用于当期望位置在小于预定数量的可变长度码时终止代码可用。

35. 发明授权

US07046735B2 Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes 有权
标题翻译：用于将数据调制和解调为可变长度代码并向代码串提供同步信号的方法和装置
公开(公告)号：US07046735B2
公开(公告)日：2006-05-16
申请号：US11088338
申请日：2005-03-24
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H04B14/04
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： Apparatus for modulating data having a basic data length of m bits, to a variable-length code (d, k; m, n; r) having a basic code length of n bits. A sync signal is added to a received train of codes after a minimum run. The sync signal has a pattern that is repeated twice continuously. The minimum run is repeated no more than six times; and the sync signal exhibits seven types of sync signal IDs, with any adjacent two bits of a sync signal ID being spaced apart by a distance of 2.
摘要翻译：用于将具有m位的基本数据长度的数据调制为具有n位的基本码长度的可变长度码（d，k; m，n; r）的装置。在最小运行之后，将同步信号添加到接收到的代码序列。同步信号具有连续重复两次的图案。最小运行重复不超过六次; 并且同步信号表现出七种类型的同步信号ID，同步信号ID的任何相邻的两个比特间隔开2的距离。

36. 发明授权

US06983022B2 Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes 失效
标题翻译：用于将数据调制和解调为可变长度代码并向代码串提供同步信号的方法和装置
公开(公告)号：US06983022B2
公开(公告)日：2006-01-03
申请号：US11077878
申请日：2005-03-10
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H04B14/04
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A data-modulating apparatus for modulating data having a basic data length of m bits, to a variable-length code(d, k; m, n: r) having a basic code length of n bits. A sync signal is added to a recieved train of codes after a minimum run, the sync signal having a pattern that breaks a maximum run. The pattern is repeated twice continuously, and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in the termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.
摘要翻译：一种用于将具有m比特的基本数据长度的数据调制为具有n比特的基本码长度的可变长度码（d，k; m，n：r）的数据调制装置。在最小运行之后，将同步信号添加到接收的代码序列，同步信号具有中断最大运行的模式。该图案连续重复两次，最小运行重复不超过六次。当紧接在同步信号之前的调制码序列包括在终止表中时，同步信号的第一位为“1”，用于当期望位置在小于预定数量的可变长度码时终止代码可用。

37. 发明申请

US20050168355A1 Method and apparatus for modulating and demodulating data into a variable length code and a providing medium for implementing the method 有权
公开(公告)号：US20050168355A1
公开(公告)日：2005-08-04
申请号：US11088464
申请日：2005-03-24
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H03M7/14 , G11B20/14 , H03M5/14 , H04L7/00 , H04L7/04 , H03M7/00 , H03M7/40
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

38. 发明申请

US20050162291A1 Method and apparatus for modulating and demodulating data into a variable length code and a providing medium for implementing the method 有权
公开(公告)号：US20050162291A1
公开(公告)日：2005-07-28
申请号：US11088350
申请日：2005-03-24
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H03M7/14 , G11B20/14 , H03M5/14 , H04L7/00 , H04L7/04 , H03M7/00
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

39. 发明授权

US06225921B1 Device for encoding/decoding n-bit source words into corresponding m-bit channel words, and vice versa 有权
标题翻译：将n位源字编码/解码为相应的m位通道字的装置，反之亦然
公开(公告)号：US06225921B1
公开(公告)日：2001-05-01
申请号：US09177957
申请日：1998-10-23
申请人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara , Kousuke Nakamura
发明人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara , Kousuke Nakamura
IPC分类号： H03M500
CPC分类号： G11B20/1426 , H03M5/145
摘要： A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C) satisfying a (d,k) constraint, wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (Y1, Y2, Y2). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity preserving (table I). The relations hold that m>n≧1, p≧1, and that p can vary. Preferably, m=n+1. Further, a sync word generator (9) is available for generating a q-bit sync word also satisfying said (d,k) constraint, the said sync word starting with a ‘0’ bit and ending with a ‘0’ bit, the device further comprising merging means (19) for merging said sync word in said stream of databits of the binary channel signal, and that q is an integer value larger than k. (FIG. 1) Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.
摘要翻译：公开了一种用于将二进制源信号（S）的数据位流编码为满足（d，k）约束的二进制信道信号（C）的数据位流的装置，其中源信号的比特流被分为 n位源字（x1，x2），该装置包括适于将所述源字转换成对应的m位通道字（Y1，Y2，Y2）的转换装置（CM）。转换装置（CM）还适于将n位源字转换成相应的m位通道字，使得每个n位源字的转换是奇偶校验（表I）。关系认定m> n> = 1，p> = 1，p可以变化。优选地，m = n + 1。此外，同步字生成器（9）可用于生成也满足所述（d，k）约束的q位同步字，所述同步字以“0”位开始并以“0”位结束，装置还包括用于在所述二进制信道信号的所述数据位流中合并所述同步字，并且所述q是大于k的整数值的合并装置（19）。（图1）此外，公开了一种解码装置，用于对通过编码装置获得的信道信号进行解码。

40. 发明授权

US5528236A Modulating method, demodulating method, modulating apparatus, and demodulating apparatus 失效
标题翻译：调制方法，解调方法，调制装置和解调装置
公开(公告)号：US5528236A
公开(公告)日：1996-06-18
申请号：US213234
申请日：1994-03-15
申请人： Yoshihide Shimpuku , Toshiyuki Nakagawa
发明人： Yoshihide Shimpuku , Toshiyuki Nakagawa
IPC分类号： G11B20/14 , H03M5/14 , H03M7/14 , H04N5/926 , H04N5/945 , H03M7/46
CPC分类号： G11B20/1426 , H03M5/145 , H04N5/9261 , H04N5/945
摘要： A modulating system for converting data of a basic data length of m bits into a variable length code (d, k; m, n; r) of a basic code length of n bits, which comprises the steps of: judging a binding length i (i=1.about.r) of the basic data; uniformly converting data of m.times.i bits into a code of n.times.r bits by using a conversion table for converting data of m.times.r bits where the binding length i is the maximum binding length r, and including at least one conversion table where the binding length i is less than r; and taking out specific bits from the code of n.times.r bits thus obtained on the basis of the judged binding length i to output them as a modulation code. There is also a demodulating system for converting, in reverse direction, a variable length code (d, k; m, n; r) of a basic code length of n bits into data of a basic data length of m bits, comprising the steps of: judging a binding length i of the variable length code; uniformly converting, in reverse direction, a variable length code of n.times.i bits into data of m.times.r bits by a reverse conversion table for converting, in reverse direction, a variable length code of n.times.r bits where the binding length i is the maximum binding length r, and including at least one reverse conversion table where the binding length i is less than r; and taking out specific bits from data thus obtained on the basis of the judged binding length i to output it as reproduction data.
摘要翻译：一种用于将m位的基本数据长度的数据转换成n位基本码长度的可变长度码（d，k; m，n; r）的调制系统，包括以下步骤：判断装订长度i （i = 1 DIFFERENCE r）的基本数据; 通过使用用于转换mxr位的数据的转换表将mxi位的数据均匀地转换成nxr位的码，其中绑定长度i是最大绑定长度r，并且包括至少一个转换表，其中绑定长度i小于 ; 并且根据所判定的绑定长度i从由此获得的n×r位的代码中取出特定位，以将其作为调制码输出。还有一个解调系统，用于将n位基本码长度的可变长度码（d，k; m，n; r）转换成m位基本数据长度的数据，反向地包括步骤判断可变长度码的绑定长度i; 通过反向转换表将nxi位的可变长度码以相反方向均匀地转换成mxr位的数据，用于在相反方向上转换nxr位的可变长度码，其中绑定长度i是最大绑定长度r，并且包括至少一个反向转换表，其中绑定长度i小于r; 并且根据所判定的装订长度i从由此获得的数据中取出特定的位，以将其作为再现数据输出。

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