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31. 发明申请

US20120206970A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20120206970A1
公开(公告)日：2012-08-16
申请号：US13285181
申请日：2011-10-31
申请人： Toshifumi WATANABE , Hidetoshi Saito
发明人： Toshifumi WATANABE , Hidetoshi Saito
IPC分类号： G11C16/04
CPC分类号： G11C7/222 , G11C16/10 , G11C16/32
摘要： According to one embodiment, an interface includes first to third input circuits, delay and selection circuits. The first input circuit outputs an active first internal signal in response to an active first control signal received by a memory device. The second input circuit outputs an active second internal signal in response to an active second control signal received by the device while the device is receiving the active first control signal. The delay circuit outputs a selection signal in first or second states after the elapse of a first period from inactivation or activation of the first control signal. The selection circuit outputs the first and second internal signals as an enable signal while receiving the selection signal of the first and second states. The third input circuit outputs an input signal received from the outside from the interface to inside the device while receiving the active enable signal.
摘要翻译：根据一个实施例，接口包括第一至第三输入电路，延迟和选择电路。第一输入电路响应于由存储器件接收到的有效的第一控制信号而输出有效的第一内部信号。第二输入电路响应于设备在接收到有效的第一控制信号时接收到的有效的第二控制信号而输出有效的第二内部信号。延迟电路在从第一控制信号的失活或激活开始经过第一周期之后，输出第一或第二状态的选择信号。选择电路在接收第一和第二状态的选择信号的同时，将第一和第二内部信号作为使能信号输出。第三输入电路在接收到有效使能信号的同时，将从外部接收的输入信号输出到设备内部。

32. 发明授权

US08089454B2 Driving circuit for electrophoretic display device, electrophoretic display device, method for driving the same, and electronic apparatus 有权
标题翻译：电泳显示装置的驱动电路，电泳显示装置及其驱动方法以及电子装置
公开(公告)号：US08089454B2
公开(公告)日：2012-01-03
申请号：US12366919
申请日：2009-02-06
申请人： Hidetoshi Saito
发明人： Hidetoshi Saito
IPC分类号： G09G3/34
CPC分类号： G09G3/344 , G09G2300/0857 , G09G2300/0871
摘要： In an electrophoretic device including a display including pixels with electrophoretic particles between pixel and common electrodes, a pixel-switching element, a memory holding an image signal from the pixel-switching element, and a switch connecting one of first and second control lines to the pixel electrode according to a signal output according to the image signal from the memory, a driving circuit includes a holding voltage unit supplying a holding voltage holding the image signal in the memory, a pixel potential unit supplying a first pixel potential to the first control line and a different second pixel potential to the second control line, a common potential unit supplying a common potential to the common electrode, and a control unit controlling the holding potential unit, the common potential unit, and the pixel potential unit to stop the holding potential after the first and second pixel potentials and common potential are stopped.
摘要翻译：在包括像素和公共电极之间的包括具有电泳粒子的像素的显示器的电泳装置中，像素开关元件，保持来自像素开关元件的图像信号的存储器和将第一和第二控制线之一连接到像素电极，根据来自存储器的图像信号的信号输出，驱动电路包括：将保持图像信号的保持电压提供到存储器中的保持电压单元;向第一控制线提供第一像素电位的像素电位单元以及向第二控制线的不同的第二像素电位，向公共电极提供公共电位的公共电位单元以及控制保持电位单元，公共电位单元和像素电位单元以控制保持电位的控制单元在第一和第二像素电位和公共电位被停止之后。

33. 发明授权

US07998621B2 Collector, battery electrode substrate, and methods for producing the same 有权
标题翻译：集电体，电池用电极基板及其制造方法
公开(公告)号：US07998621B2
公开(公告)日：2011-08-16
申请号：US11328219
申请日：2006-01-10
申请人： Keizo Harada , Masahiro Kato , Hidetoshi Saito , Tadashi Omura , Hitoshi Tsuchida
发明人： Keizo Harada , Masahiro Kato , Hidetoshi Saito , Tadashi Omura , Hitoshi Tsuchida
IPC分类号： H01M4/66 , H01M4/70 , H01M4/80 , B32B15/085
CPC分类号： H01M4/32 , D06M11/83 , H01M4/04 , H01M4/667 , H01M4/80 , H01M4/806 , H01M2004/021 , Y10T29/10 , Y10T29/49115 , Y10T428/2958
摘要： A battery electrode substrate includes a metallic porous body. The metallic porous body has a structure in which a surface of a plastic fiber in a woven or unwoven fabric is coated with a nickel film. The nickel film coats the surface with an average coverage ratio of not less than 85%.
摘要翻译：电池电极基板包括金属多孔体。金属多孔体具有这样的结构，其中织造或非织造织物中的塑料纤维的表面涂覆有镍膜。镍膜的表面平均覆盖率不低于85％。

34. 发明授权

US07564717B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07564717B2
公开(公告)日：2009-07-21
申请号：US11923200
申请日：2007-10-24
申请人： Kazuhiko Sato , Hidetoshi Saito , Kiyotaka Uchigane
发明人： Kazuhiko Sato , Hidetoshi Saito , Kiyotaka Uchigane
IPC分类号： G11C11/34
CPC分类号： G11C16/30 , H02M3/073 , H02M2003/077
摘要： A semiconductor memory device includes a memory cell array, word lines each of which connects the control gates of the memory cells on the same row together in the memory cell array, a row decoder which selects a word line, and applies a voltage to the selected word line, and a voltage generator which generates a boosted voltage, and outputs the boosted voltage as the voltage, the voltage generator includes a comparator which compares a first voltage with a second voltage, and outputs a comparison result signal, a constant current circuit which generates a first control signal in accordance with the comparison result signal, a first delay circuit which generates a second control signal by delaying the comparison result signal, and a charge pump circuit which generates the boosted voltage in response to the first and second control signals.
摘要翻译：一种半导体存储器件，包括一个存储单元阵列，每个都将存储单元阵列中同一行上的存储单元的控制栅极连接在一起的字线，选择字线的行译码器，字线和产生升压电压的电压发生器，并输出升压电压作为电压，电压发生器包括将第一电压与第二电压进行比较的比较器，并输出比较结果信号;恒流电路，根据比较结果信号产生第一控制信号，通过延迟比较结果信号产生第二控制信号的第一延迟电路和响应于第一和第二控制信号产生升压电压的电荷泵电路。

35. 发明申请

US20060159998A1 Collector, battery electrode substrate, and methods for producing the same 有权
标题翻译：集电体，电池用电极基板及其制造方法
公开(公告)号：US20060159998A1
公开(公告)日：2006-07-20
申请号：US11328219
申请日：2006-01-10
申请人： Keizo Harada , Masahiro Kato , Hidetoshi Saito , Tadashi Omura , Hitoshi Tsuchida
发明人： Keizo Harada , Masahiro Kato , Hidetoshi Saito , Tadashi Omura , Hitoshi Tsuchida
IPC分类号： H01M4/80 , H01M4/66 , B32B15/085 , B05D5/12
CPC分类号： H01M4/32 , D06M11/83 , H01M4/04 , H01M4/667 , H01M4/80 , H01M4/806 , H01M2004/021 , Y10T29/10 , Y10T29/49115 , Y10T428/2958
摘要： A collector that has enough hardness and flexibility and a battery electrode substrate that uses this collector are provided. Also provided is a low-cost battery electrode substrate that exhibits excellent high-rate charge/discharge characteristics and low electrical resistance and that is able to avoid the decline in cycle characteristics caused by repetitive charging/discharging. The invention is a battery electrode substrate having a structure in which a nickel film is coated on the surface of plastic fiber of a woven or unwoven fabric, wherein a metallic porous body in which the average coverage ratio by the nickel film is not less than 85% is used. The invention is also a collector comprising a metallic porous body having a structure in which a surface of plastic fiber of a woven or unwoven fabric is coated with a nickel film so as to be an average coverage ratio of not less than 85%, wherein the metallic porous body comprises at least two layers of a lower density region and a higher density region in the thickness direction between which there is a difference in density of included nickel, and a thickness of the lower density region is not less than 1.5-times a thickness of the higher density region. The invention is also a battery electrode substrate that has a structure in which a surface of a plastic fiber in a unwoven fabric is coated with a nickel film, wherein the battery electrode substrate uses a metallic porous body in which a transverse-to-longitudinal ratio of the electrical resistance is not less than two times. The plastic fiber is preferably a fiber that has a core/sheath composite fiber structure in which the core is polypropylene and the sheath is polyethylene.
摘要翻译：提供具有足够的硬度和柔性的收集器以及使用该收集器的电池电极基板。还提供了一种低成本的电池电极基板，其表现出优异的高速率充放电特性和低电阻，并且能够避免由重复的充电/放电引起的循环特性的下降。本发明是一种电池电极基板，其具有将镍膜涂布在机织或非织造织物的塑料纤维的表面上的结构，其中，镍膜的平均覆盖率不小于85的金属多孔体％用来。本发明也是一种包含金属多孔体的收集器，该金属多孔体具有这样的结构，其中织造或非织造织物的塑料纤维的表面被镍膜涂覆，以使其平均覆盖率不小于85％，其中金属多孔体包括至少两层厚度方向上的较低密度区域和较高密度区域，其间存在所包含的镍的密度差，并且较低密度区域的厚度不小于1.5倍较高密度区域的厚度。本发明也是一种电池电极基板，其具有以下结构：无纺布中的塑料纤维的表面被镍膜覆盖，其中，电池电极基板使用金属多孔体，其中横向纵向比的电阻不小于2次。塑料纤维优选是具有芯/皮复合纤维结构的纤维，其中芯是聚丙烯，护套是聚乙烯。

36. 发明授权

US06920057B2 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US06920057B2
公开(公告)日：2005-07-19
申请号：US10860275
申请日：2004-06-04
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/00 , G11C5/00 , G11C8/12 , G11C16/10 , G11C16/26 , G11C5/02
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

37. 发明授权

US06903983B2 Semiconductor integrated circuit device and read start trigger signal generating method therefor 有权
标题翻译：半导体集成电路器件及其读取开始触发信号产生方法
公开(公告)号：US06903983B2
公开(公告)日：2005-06-07
申请号：US10325753
申请日：2002-12-23
申请人： Tokumasa Hara , Hidetoshi Saito , Hitoshi Shiga , Yasuhiko Honda , Tadayuki Taura , Hideo Kato
发明人： Tokumasa Hara , Hidetoshi Saito , Hitoshi Shiga , Yasuhiko Honda , Tadayuki Taura , Hideo Kato
IPC分类号： G11C16/02 , G11C8/18 , G11C16/32 , G11C16/04
CPC分类号： G11C8/18 , G11C16/32 , G11C2216/22
摘要： A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank 0 or bank 1 and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.
摘要翻译：半导体集成电路装置包括对应于存储体0的第一存储单元阵列，对应于存储体1的第二存储单元阵列，检测输入地址的转换并产生第一地址转换信号的第一地址转换信号产生电路，第二地址转换信号生成电路，其预先检测存储体0或存储体1的自动执行结束并产生第二地址转换信号，以及读取开始触发输出电路。读取开始触发输出电路基于第一地址转换信号和第二地址转换信号输出读取开始触发信号。

38. 发明授权

US06810575B1 Functional element for electric, electronic or optical device and method for manufacturing the same 失效
标题翻译：电气，电子或光学装置的功能元件及其制造方法
公开(公告)号：US06810575B1
公开(公告)日：2004-11-02
申请号：US09647489
申请日：2000-09-29
申请人： Hidetoshi Saito , Minoru Sato , Yoshikazu Ueda , Hideo Kinoshita
发明人： Hidetoshi Saito , Minoru Sato , Yoshikazu Ueda , Hideo Kinoshita
IPC分类号： H01L31036
CPC分类号： H01L29/0665 , B82Y10/00 , C30B25/00 , C30B25/005 , C30B29/16 , C30B29/62 , H01J9/025 , H01L29/0673 , Y10T29/41 , Y10T29/417 , Y10T29/49002 , Y10T29/49105
摘要： Disclosed is a functional element for use in an electric, an electronic or an optical device, and a method for producing the same. The functional element comprises a substrate having on an upper surface thereof a plurality of metal oxide needles extending upwardly of the upper surface of the substrate, with their respective central axes arranged substantially in parallel with each other, wherein the needles have a specific average circle-based diameter and a specific average aspect ratio, and wherein the needles are present at a specific density at the upper surface of the substrate. Also disclosed is a method for producing the functional element, which comprises gasifying a metal compound having the capability to react with an oxide-forming substance to form a metal oxide, to thereby obtain a metal compound gas, and applying the obtained metal compound gas onto a surface of a substrate which is placed in a reaction zone containing the oxide-forming substance and which is heated to a temperature higher than the temperature of the metal compound gas.
摘要翻译：公开了一种用于电气，电子或光学装置的功能元件及其制造方法。所述功能元件包括在其上表面上具有从所述基板的上表面向上延伸的多个金属氧化物针的基板，其各自的中心轴彼此基本平行地布置，其中所述针具有特定的平均圆形 - 基准直径和特定的平均纵横比，并且其中针在基底的上表面处以特定的密度存在。还公开了一种功能元件的制造方法，其特征在于，使具有与形成氧化物的物质反应形成金属氧化物的金属化合物气化，从而得到金属化合物气体，将得到的金属化合物气体将基板的表面放置在含有氧化物形成物质的反应区中，并将其加热到高于金属化合物气体的温度的温度。

39. 发明授权

US06808688B1 Particulate trap for diesel engine 失效
标题翻译：柴油发动机颗粒捕集器
公开(公告)号：US06808688B1
公开(公告)日：2004-10-26
申请号：US09597558
申请日：2000-06-20
申请人： Hidetoshi Saito , Masataka Oji
发明人： Hidetoshi Saito , Masataka Oji
IPC分类号： B01D5334
CPC分类号： F01N3/022 , F01N3/0217 , F01N3/023 , F01N3/035 , F01N3/2803 , F01N2330/14 , F01N2340/02 , F01N2570/14 , Y02A50/2322 , Y10S55/30
摘要： A particulate trap that burns and removes particulate matters (particles, consisting mainly of carbon particles, contained in the exhaust gas of a diesel engine of a car) trapped by a filter without using a specifically provided heat source such as a burner or an electric heater even when the car is running in ordinary urban areas, i.e., when the exhaust gas is low in temperature. In the particulate trap, a catalytic converter 3, formed of a metallic porous body having a three-dimensional network structure, carrying an oxidizing catalyst is placed upstream of a filter 4 that traps particulate matters. The catalytic converter 3 oxidizes NO in the exhaust gas into NO2, which in turn burns and removes particulate matters trapped by the filter 4.
摘要翻译：一种颗粒捕集器，其不使用特定设置的热源（例如燃烧器或电加热器）燃烧和除去由过滤器捕获的颗粒物质（主要由碳颗粒组成的，包含在汽车的柴油发动机的废气中的颗粒）即使汽车正在普通的市区运行，即当排气温度低时也是如此。在颗粒捕集器中，由具有三维网状结构的带有氧化催化剂的金属多孔体形成的催化转化器3放置在捕集颗粒物质的过滤器4的上游。催化转化器3将废气中的NO氧化成NO2，其又燃烧并除去由过滤器4捕获的颗粒物质。

40. 发明授权

US06717852B2 Nonvolatile semiconductor memory device capable of concurrently and reliably writing/erasing and reading memory cores 有权
标题翻译：能够同时且可靠地写入/擦除和读取存储器核的非易失性半导体存储器件
公开(公告)号：US06717852B2
公开(公告)日：2004-04-06
申请号：US10267693
申请日：2002-10-10
申请人： Yasuhiko Honda , Hideo Kato , Masao Kuriyama , Hidetoshi Saito , Tokumasa Hara
发明人： Yasuhiko Honda , Hideo Kato , Masao Kuriyama , Hidetoshi Saito , Tokumasa Hara
IPC分类号： G11C1632
CPC分类号： G11C16/08 , G11C7/1042 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor memory device, which allows concurrent execution of a write/erase operation and a read operation, is provided for each core with a core busy output circuit which has a function of, at the start, end, suspending or resuming of a write/erase operation, setting the sequence in which a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are set or reset so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.
摘要翻译：为每个核心提供一个允许并行执行写入/擦除操作和读取操作的半导体存储器件，其具有核心忙输出电路，其具有在开始和结束时挂起或恢复写/ 擦除操作，设置写入/擦除或从内核读取的命令的顺序，指示核心是否被选择的核心选择信号以及指示核心处于写/擦除模式的忙信号被设置或复位，使得在写入/擦除操作中的核心和读取操作中的核心不会发生多次选择。

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