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31. 发明授权

US09304174B1 Cross-coupled voltage and temperature monitoring in programmable integrated circuits 有权
标题翻译：可编程集成电路中的交叉耦合电压和温度监控
公开(公告)号：US09304174B1
公开(公告)日：2016-04-05
申请号：US14463560
申请日：2014-08-19
申请人： Xilinx, Inc.
发明人： Bradley L. Taylor , Sagheer Ahmad
IPC分类号： H03K19/177 , G06F1/00 , G01R31/40 , G01R17/02 , G01R19/00 , G01K17/00
CPC分类号： G01R31/40 , G01K3/005 , G01K17/00 , G01R17/02 , G01R19/0084 , H03K19/177 , H03K19/17784
摘要： Method and apparatus for monitoring system operations in an integrated circuit. A method includes receiving a first power supply voltage from a first processing domain, comparing the first power supply voltage to a first reference voltage, receiving the second power supply voltage from the second processing domain, comparing the second power supply voltage to a second reference voltage, determining that the first power supply voltage exceeds the first reference voltage or that the second power supply voltage exceeds the second reference voltage, and transmitting one or more alarms corresponding to one or more of the first power supply voltage and the second power supply voltage in response to determining that the first power supply voltage exceeds the first reference voltage or that the second power supply voltage exceeds the second reference voltage. An integrated circuit and system monitor are also provided.
摘要翻译：用于监控集成电路中的系统操作的方法和装置。一种方法包括从第一处理域接收第一电源电压，将第一电源电压与第一参考电压进行比较，从第二处理域接收第二电源电压，将第二电源电压与第二参考电压确定所述第一电源电压超过所述第一参考电压或者所述第二电源电压超过所述第二参考电压，并且将与所述第一电源电压和所述第二电源电压中的一个或多个相对应的一个或多个警报发送到响应于确定第一电源电压超过第一参考电压或第二电源电压超过第二参考电压。还提供集成电路和系统监视器。

32. 发明授权

US08937496B1 Clock monitor 有权
标题翻译：时钟监视器
公开(公告)号：US08937496B1
公开(公告)日：2015-01-20
申请号：US14464661
申请日：2014-08-20
申请人： Xilinx, Inc.
发明人： Sagheer Ahmad , Alex S. Warshofsky , Ygal Arbel
IPC分类号： G01R23/02 , H03D3/00 , H03K9/06 , H03K5/19
CPC分类号： H03K5/19
摘要： A clock monitoring circuit is disclosed. The clock monitoring circuit is configured to receive first and second clock signals generated in respective clock domains. The clock monitoring circuit includes a first counter configured to count clock cycles of the first clock signal for a first period of time delineated by clock cycles of the second clock signal. The first counter outputs a count value indicating the number of counted clock cycles. The clock monitoring circuit also includes a threshold comparator circuit configured to generate an error signal in response to expiration of the first period of time and the first count value output by the first counter falling outside of an expected range.
摘要翻译：公开了一种时钟监控电路。时钟监视电路被配置为接收在各个时钟域中产生的第一和第二时钟信号。时钟监视电路包括第一计数器，其被配置为对由第二时钟信号的时钟周期描绘的第一时间段对第一时钟信号的时钟周期进行计数。第一计数器输出指示计数时钟周期数的计数值。时钟监视电路还包括阈值比较器电路，该阈值比较器电路被配置为响应于第一时间段的期满和由第一计数器输出的第一计数值落在期望范围之外而产生误差信号。

33. 发明授权

US12093394B2 System and method for secure deconstruction sensor in a heterogeneous integration circuitry 有权
公开(公告)号：US12093394B2
公开(公告)日：2024-09-17
申请号：US18111808
申请日：2023-02-20
申请人： XILINX, INC.
发明人： Aman Gupta , James D. Wesselkamper , James Anderson , Nader Sharifi , Ahmad R. Ansari , Sagheer Ahmad , Brian C. Gaide
IPC分类号： G06F21/57 , H04L9/06 , H04L9/08 , H04L9/14 , H04L9/30
CPC分类号： G06F21/575 , H04L9/0618 , H04L9/0822 , H04L9/0861 , H04L9/14 , H04L9/30 , G06F2221/034
摘要： Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.

34. 发明授权

US12047275B2 Efficiency and quality of service improvements for systems with higher bandwidth clients mixed with lower bandwidth clients 有权
公开(公告)号：US12047275B2
公开(公告)日：2024-07-23
申请号：US17705087
申请日：2022-03-25
申请人： XILINX, INC.
发明人： Aman Gupta , Jaideep Dastidar , Jeffrey Cuppett , Sagheer Ahmad
IPC分类号： H04L45/24 , H04L45/74 , H04L49/109
CPC分类号： H04L45/24 , H04L45/74 , H04L49/109
摘要： Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.

35. 发明授权

US12019576B2 Systems and methods to transport memory mapped traffic amongst integrated circuit devices 有权
公开(公告)号：US12019576B2
公开(公告)日：2024-06-25
申请号：US17879675
申请日：2022-08-02
申请人： XILINX, INC.
发明人： Krishnan Srinivasan , Ygal Arbel , Sagheer Ahmad , Abbas Morshed
IPC分类号： G06F13/40
CPC分类号： G06F13/4027 , G06F2213/40
摘要： Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.

36. 发明授权

US11892966B2 Multi-use chip-to-chip interface 有权
公开(公告)号：US11892966B2
公开(公告)日：2024-02-06
申请号：US17551132
申请日：2021-12-14
申请人： XILINX, INC.
发明人： Krishnan Srinivasan , Ygal Arbel , Sagheer Ahmad
IPC分类号： G06F13/36 , G06F13/42
CPC分类号： G06F13/4282 , G06F2213/0016
摘要： Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

37. 发明授权

US11683038B1 Adaptive integrated programmable device platform 有权
公开(公告)号：US11683038B1
公开(公告)日：2023-06-20
申请号：US17350639
申请日：2021-06-17
申请人： Xilinx, Inc.
发明人： Sagheer Ahmad , Jaideep Dastidar , Brian C. Gaide , Juan J. Noguera Serra , Ian A. Swarbrick
IPC分类号： H03K19/17728 , H03K19/17736 , H03K19/17704
CPC分类号： H03K19/17728 , H03K19/17736 , H03K19/17712
摘要： A System-on-Chip includes a first partition configured to implement a first application using of at least a first portion of one or more of a plurality of subsystems of the System-on-Chip and a second partition configured to implement a second application concurrently with the first partition. The second application uses at least a second portion of one or more of the plurality of subsystems. The first partition is isolated from the second partition.

38. 发明公开

US20230153156A1 SYNCHRONIZATION OF SYSTEM RESOURCES IN A MULTI-SOCKET DATA PROCESSING SYSTEM 审中-公开
公开(公告)号：US20230153156A1
公开(公告)日：2023-05-18
申请号：US17455074
申请日：2021-11-16
申请人： Xilinx, Inc.
发明人： Karthik Shankar , Jaideep Dastidar , Ahmad R. Ansari , Sagheer Ahmad
IPC分类号： G06F9/50
CPC分类号： G06F9/5027
摘要： Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.

39. 发明授权

US11182110B1 On-chip memory block circuit 有权
公开(公告)号：US11182110B1
公开(公告)日：2021-11-23
申请号：US16547550
申请日：2019-08-21
申请人： Xilinx, Inc.
发明人： Ahmad R. Ansari , Sagheer Ahmad
IPC分类号： G06F3/06 , H03K19/17728 , G11C5/14 , G11C7/22 , G11C11/4076 , G06F5/06 , G06F13/16 , G06F1/3206 , G11C7/24 , H03K19/173
摘要： A memory block circuit can include a plurality of data interfaces, a switch connected to each data interface of the plurality of data interfaces, and a plurality of memory banks each coupled to the switch. Each memory bank can include a memory controller and a random access memory connected to the memory controller. The memory block circuit also includes a control interface and a management controller connected to the control interface and each memory bank of the plurality of memory banks. Each memory bank can be independently controlled by the management controller.

40. 发明授权

US10673439B1 Adaptive integrated programmable device platform 有权
公开(公告)号：US10673439B1
公开(公告)日：2020-06-02
申请号：US16367108
申请日：2019-03-27
申请人： Xilinx, Inc.
发明人： Sagheer Ahmad , Jaideep Dastidar , Brian C. Gaide , Juan J. Noguera Serra , Ian A. Swarbrick
IPC分类号： H03K19/17728 , H03K19/17736 , H03K19/17704
摘要： A device can include programmable logic circuitry, a processor system coupled to the programmable logic circuitry, and a network-on-chip. The network-on-chip is coupled to the programmable logic circuitry and the processor system. The network-on-chip is programmable to establish user specified data paths communicatively linking a circuit block implemented in the programmable logic circuitry and the processor system. The programmable logic circuitry, the network-on-chip, and the processor system are configured using a platform management controller.

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