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31. 发明授权

US06940302B1 Integrated circuit output driver circuitry with programmable preemphasis 有权
标题翻译：具有可编程预加重功能的集成电路输出驱动器电路
公开(公告)号：US06940302B1
公开(公告)日：2005-09-06
申请号：US10338921
申请日：2003-01-07
申请人： Sergey Y. Shumarayev , Thomas H. White , Rakesh H. Patel , Wilson Wong
发明人： Sergey Y. Shumarayev , Thomas H. White , Rakesh H. Patel , Wilson Wong
IPC分类号： H03K19/0185 , H03K19/177 , H04L25/02 , H03K17/16
CPC分类号： H03K19/17744 , H03K19/018585 , H03K19/1778 , H04L25/0272 , H04L25/0286
摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.
摘要翻译：提供了具有差分I / O电路的可编程逻辑器件集成电路。差分I / O电路可以包括用于在输出线对之间提供差分数字输出数据信号的输出驱动器。用户可以对I / O电路进行编程，以适应不同的高速差分I / O信号标准。用户还可以对I / O电路进行编程，以向输出数据信号提供期望量的预加重。

32. 发明授权

US06252422B1 Overvoltage-tolerant interface for intergrated circuits 有权
标题翻译：集成电路的过压容限接口
公开(公告)号：US06252422B1
公开(公告)日：2001-06-26
申请号：US09400953
申请日：1999-09-22
申请人： Rakesh H. Patel , John E. Turner , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , Wilson Wong
IPC分类号： H03K190175
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.
摘要翻译：一种用于直接与在输入/输出驱动器的电源电压（817）之上的焊盘（820）处的电压直接接口的输入/输出驱动器。这可能被称为“过电压条件”。例如，如果电源电压为3.3V，则可以在输入/输出驱动器的焊盘处提供5V电压信号。输入/输出驱动器将容忍该电压电平并防止漏电流路径。这将提高集成电路的性能，可靠性和使用寿命。输入/输出驱动器包括用于防止泄漏电流路径的阱偏压发生器（1002）。

33. 发明授权

US06724222B2 Programmable logic with lower internal voltage circuitry 失效
标题翻译：具有较低内部电压电路的可编程逻辑
公开(公告)号：US06724222B2
公开(公告)日：2004-04-20
申请号：US10366814
申请日：2003-02-13
申请人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
IPC分类号： H03K19175
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： A technique and circuitry interfaces a programmable logic integrated circuit compatible with one voltage level to other integrated circuits compatible with a different voltage level. In particular, an on-chip voltage less than the external supply level of the programmable logic integrated circuit is provided to a core portion of a programmable logic integrated circuit by way of a conversion transistor. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. Externally, the programmable logic integrated circuit will interface with an external supply voltage level. The input and output signals to and from the programmable logic integrated circuit will be compatible with the external supply level.
摘要翻译：技术和电路将与一个电压电平兼容的可编程逻辑集成电路与不同电压电平兼容的其他集成电路接口。特别地，通过转换晶体管将可编程逻辑集成电路的小于外部电源电平的片上电压提供给可编程逻辑集成电路的核心部分。在一个实施例中，转换晶体管的布局（或物理结构）分布在芯部分周围。在外部，可编程逻辑集成电路将与外部电源电压接口。来自可编程逻辑集成电路的输入和输出信号将与外部电源电平兼容。

34. 发明授权

US06583646B1 Overvoltage-tolerant interface for integrated circuits 有权
标题翻译：集成电路的过压容限接口
公开(公告)号：US06583646B1
公开(公告)日：2003-06-24
申请号：US09860028
申请日：2001-05-16
申请人： Rakesh H. Patel , John E. Turner , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , Wilson Wong
IPC分类号： H03K190175
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： An input/output driver for interfacing directly with a voltage at a pad which is above a supply voltage for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator for preventing leakage current paths.
摘要翻译：一个输入/输出驱动器，用于直接与焊盘上的电压进行接口，该电压高于输入/输出驱动器的电源电压。这可能被称为“过电压条件”。例如，如果电源电压为3.3V，则可以在输入/输出驱动器的焊盘处提供5V电压信号。输入/输出驱动器将容忍该电压电平并防止漏电流路径。这将提高集成电路的性能，可靠性和使用寿命。输入/输出驱动器包括用于防止漏电流路径的阱偏置发生器。

35. 发明授权

US06563343B1 Circuitry for a low internal voltage 有权
标题翻译：电路内部电压低
公开(公告)号：US06563343B1
公开(公告)日：2003-05-13
申请号：US10136944
申请日：2002-04-30
申请人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
IPC分类号： H03K190175
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.
摘要翻译：一种技术通过转换晶体管向集成电路的核心部分提供片上电压。片上电压可能是内部电压降低，小于集成电路的VCC。在一个实施例中，转换晶体管的布局（或物理结构）分布在芯部分周围。通过为内核提供降低的电压，集成电路可以与与不同电压电平兼容的其他集成电路接口。

36. 发明授权

US06414518B1 Circuitry for a low internal voltage integrated circuit 有权
标题翻译：用于集成电路的结构，以提供片上电压
公开(公告)号：US06414518B1
公开(公告)日：2002-07-02
申请号：US09449166
申请日：1999-11-24
申请人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
IPC分类号： H03K1900
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.
摘要翻译：一种技术通过转换晶体管向集成电路的核心部分提供片上电压。片上电压可能是内部电压降低，小于集成电路的VCC。在一个实施例中，转换晶体管的布局（或物理结构）分布在芯部分周围。通过为内核提供降低的电压，集成电路可以与与不同电压电平兼容的其他集成电路接口。

37. 发明授权

US08537954B2 Method and apparatus for multi-mode clock data recovery 有权
标题翻译：多模时钟数据恢复的方法和装置
公开(公告)号：US08537954B2
公开(公告)日：2013-09-17
申请号：US12688617
申请日：2010-01-15
申请人： Sergey Y. Shumarayev , Rakesh H. Patel , Wilson Wong , Tim T. Hoang
发明人： Sergey Y. Shumarayev , Rakesh H. Patel , Wilson Wong , Tim T. Hoang
IPC分类号： H03D3/24
CPC分类号： H03L7/0998 , H03L7/081 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/0025 , H04L7/0083 , H04L7/033
摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.
摘要翻译：所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。（CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。

38. 发明授权

US07590207B1 Modular serial interface in programmable logic device 有权
标题翻译：可编程逻辑器件中的模块化串行接口
公开(公告)号：US07590207B1
公开(公告)日：2009-09-15
申请号：US11256346
申请日：2005-10-20
申请人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim Tri Hoang , William Bereza
发明人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim Tri Hoang , William Bereza
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H04J3/0688 , H04L7/033
摘要： A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.
摘要翻译：用于可编程逻辑器件的串行接口可以用作传统的高速四边形接口，但是也允许单独的通道（如果不另外使用）被可编程地配置为环路电路（例如，锁相环）。这是通过禁用通道中的时钟数据恢复电路的数据循环来实现的，并且重新配置参考环路以用作循环电路。此外，不是提供具有四个通道的高速四边形接口和一个或多个时钟管理单元（CMU），而是可以提供具有五个或更多个通道的更灵活的接口，并且当希望将接口用作高速四通道接口，一个或多个通道可以配置为循环电路，用作CMU。

39. 发明授权

US07307446B1 Integrated circuit output driver circuitry with programmable preemphasis 有权
标题翻译：具有可编程预加重功能的集成电路输出驱动器电路
公开(公告)号：US07307446B1
公开(公告)日：2007-12-11
申请号：US11510514
申请日：2006-08-24
申请人： Sergey Y. Shumarayev , Thomas H. White , Rakesh H. Patel , Wilson Wong
发明人： Sergey Y. Shumarayev , Thomas H. White , Rakesh H. Patel , Wilson Wong
IPC分类号： H03K17/16
CPC分类号： H03K19/018585 , H03K5/06 , H03K5/13 , H03K5/151 , H03K2005/00032 , H03K2005/00065
摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.
摘要翻译：提供了具有差分I / O电路的可编程逻辑器件集成电路。差分I / O电路可以包括用于在输出线对之间提供差分数字输出数据信号的输出驱动器。用户可以对I / O电路进行编程，以适应不同的高速差分I / O信号标准。用户还可以对I / O电路进行编程，以向输出数据信号提供期望量的预加重。

40. 发明授权

US07109743B2 Integrated circuit output driver circuitry with programmable preemphasis 有权
标题翻译：具有可编程预加重功能的集成电路输出驱动器电路
公开(公告)号：US07109743B2
公开(公告)日：2006-09-19
申请号：US11148046
申请日：2005-06-07
申请人： Sergey Y Shumarayev , Thomas H White , Rakesh H Patel , Wilson Wong
发明人： Sergey Y Shumarayev , Thomas H White , Rakesh H Patel , Wilson Wong
IPC分类号： H03K17/16
CPC分类号： H03K19/17744 , H03K19/018585 , H03K19/1778 , H04L25/0272 , H04L25/0286
摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.
摘要翻译：提供了具有差分I / O电路的可编程逻辑器件集成电路。差分I / O电路可以包括用于在输出线对之间提供差分数字输出数据信号的输出驱动器。用户可以对I / O电路进行编程，以适应不同的高速差分I / O信号标准。用户还可以对I / O电路进行编程，以向输出数据信号提供期望量的预加重。

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