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31. 发明授权

US07783839B2 Using different algorithms to destage different types of data from cache 有权
标题翻译：使用不同的算法来从缓存中分配不同类型的数据
公开(公告)号：US07783839B2
公开(公告)日：2010-08-24
申请号：US11621057
申请日：2007-01-08
申请人： Binny Sher Gill , Michael Thomas Benhase , Joseph Smith Hyde, II , Thomas Charles Jarvis , Bruce McNutt , Dharmendra Shantilal Modha
发明人： Binny Sher Gill , Michael Thomas Benhase , Joseph Smith Hyde, II , Thomas Charles Jarvis , Bruce McNutt , Dharmendra Shantilal Modha
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0866 , G06F12/124 , G06F2212/502
摘要： Provided are a method, system, and article of manufacture for using different algorithms to destage different types of data from cache. A first destaging algorithm is used to destage a first type of data to a storage for a first duration. A second destaging algorithm is used to destage a second type of data to the storage for a second duration.
摘要翻译：提供了一种使用不同算法从缓存中去除不同类型的数据的方法，系统和制品。使用第一个降级算法将第一类型的数据转储到第一个持续时间的存储器。第二种去度数算法被用于在第二持续时间内将存储的第二类型的数据转移到存储器中。

32. 发明授权

US07707382B2 System and method for dynamic sizing of cache sequential list 失效
标题翻译：高速缓存序列表动态大小的系统和方法
公开(公告)号：US07707382B2
公开(公告)日：2010-04-27
申请号：US12060945
申请日：2008-04-02
申请人： Binny Sher Gill , Dharmendra Shantilal Modha
发明人： Binny Sher Gill , Dharmendra Shantilal Modha
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0866 , G06F12/123
摘要： A self-tuning, low overhead, simple to implements locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.
摘要翻译：自调整，低开销，简单实现本地自适应，新颖的缓存管理策略，动态和自适应地分级顺序和随机流中的高速缓存空间，以减少读取未命中。

33. 发明申请

US20090216944A1 EFFICIENT VALIDATION OF WRITES FOR PROTECTION AGAINST DROPPED WRITES 审中-公开
标题翻译：用于保护写作的写作的有效验证
公开(公告)号：US20090216944A1
公开(公告)日：2009-08-27
申请号：US12036194
申请日：2008-02-22
申请人： Binny Sher Gill , James Lee Hafner
发明人： Binny Sher Gill , James Lee Hafner
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F12/0866 , G06F2212/1032
摘要： A write cache provides for staging of data units written from a processor for recording in a disk. The order in which destages and validations occur is controlled to make validations more efficient. The data units are arranged in a circular queue according to their respective disk storage addresses. Each data unit is tagged with a state value of 1, 0, or −1. A destaging pointer is advanced one-by-one to each data unit like the hand of a clock. Each data unit pointed to is evaluated as a destage victim. The first step is to check its state value. A data unit newly brought into the write cache will have its state value reset to 0. It will stay that way until it receives an overwrite x command or the destage pointer clocks around to x. If an overwrite x, the state value is set to 1, in a way, indicating recent use of the data unit and postponing its destaging and eviction. If the destage pointer clocks around to x when the state was 0, then it's time to destage x and the state value is changed to −1. A write to the disk occurs and a later read will be used to verify the write. If the state value was already 1 when the destage pointer clocks around to x, the state value is reset to 0. If the destage pointer clocks around to x when the state is −1, the associated data is read from the disk and validated to be same as the copy in cache. If not, the destage of x is repeated, and the state value remains as −1. Otherwise, if the associated read for validation did return a success, then data unit x is evicted from the write cache.
摘要翻译：写高速缓存提供从处理器写入的数据单元的分段以便在盘中记录。控制出现故障和验证的顺序，使验证更有效率。数据单元根据其各自的磁盘存储地址被排列成圆形队列。每个数据单元的状态值为1，0或-1。每个数据单元像时钟的手一个接一个地提前一个命中指针。指出的每个数据单元被评估为一个流血的受害者。第一步是检查其状态值。新进入写入缓存的数据单元将其状态值重置为0.它将一直保持这种方式，直到它接收到覆盖x命令，或者指针指针周期延伸到x。如果覆盖x，状态值设置为1，表示最近使用数据单元并延迟其破坏和驱逐。如果在状态为0的情况下，目标指针周期到x，那么现在是时间到x，状态值改为-1。将发生对磁盘的写入，稍后读取将用于验证写入。如果目标指针周期到x的状态值已经为1，则状态值将重置为0.如果状态为-1，则返回指针周期为x，则从磁盘读取相关数据，并验证为与缓存中的副本相同。如果不是，则重复x的迁移，状态值保持为-1。否则，如果用于验证的关联读取确实返回成功，则数据单元x从写缓存中被逐出。

34. 发明授权

US07509470B2 System and method for dynamic sizing of cache sequential list 失效
标题翻译：高速缓存序列表动态大小的系统和方法
公开(公告)号：US07509470B2
公开(公告)日：2009-03-24
申请号：US12032851
申请日：2008-02-18
申请人： Binny Sher Gill , Dharmendra Shantilal Modha
发明人： Binny Sher Gill , Dharmendra Shantilal Modha
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0866 , G06F12/123
摘要： A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.
摘要翻译：自适应，低开销，易于实现，本地适应性，新颖的缓存管理策略，其在顺序和随机流中动态和自适应地分区高速缓存空间，从而减少读取未命中。

35. 发明申请

US20090055595A1 ADJUSTING PARAMETERS USED TO PREFETCH DATA FROM STORAGE INTO CACHE 有权
标题翻译：调整参数用于将数据从存储转入高速缓存
公开(公告)号：US20090055595A1
公开(公告)日：2009-02-26
申请号：US11843615
申请日：2007-08-22
申请人： Binny Sher Gill , Luis Angel Daniel Bathen , Steven Robert Lowe , Thomas Charles Jarvis
发明人： Binny Sher Gill , Luis Angel Daniel Bathen , Steven Robert Lowe , Thomas Charles Jarvis
IPC分类号： G06F12/02 , G06F12/12
CPC分类号： G06F12/0862 , G06F2212/1016 , G06F2212/6026
摘要： Provided are a method, system, and article of manufacture for adjusting parameters used to prefetch data from storage into cache. Data units are added from a storage to a cache, wherein requested data from the storage is returned from the cache. A degree of prefetch is processed indicating a number of data units to prefetch into the cache. A trigger distance is processed indicating a prefetched trigger data unit in the cache. The number of data units indicated by the degree of prefetch is prefetched in response to processing the trigger data unit. The degree of prefetch and the trigger distance are adjusted based on a rate at which data units are accessed from the cache.
摘要翻译：提供了一种用于调整用于将数据从存储器预取到高速缓存中的参数的方法，系统和制品。从存储器将数据单元添加到高速缓存，其中来自存储器的所请求的数据从高速缓存返回。处理一定程度的预取，指示预取到高速缓存中的数据单元的数量。处理指示缓存中的预取触发数据单元的触发距离。响应于处理触发数据单元预取由预取程度指示的数据单元的数量。基于从缓存访问数据单元的速率来调整预取程度和触发距离。

36. 发明申请

US20080140940A1 SYSTEM AND METHOD FOR DYNAMIC SIZING OF CACHE SEQUENTIAL LIST 失效
公开(公告)号：US20080140940A1
公开(公告)日：2008-06-12
申请号：US12033105
申请日：2008-02-19
申请人： Binny Sher Gill , Dharmendra Shantilal Modha
发明人： Binny Sher Gill , Dharmendra Shantilal Modha
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0866 , G06F12/123
摘要： A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.

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