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31. 发明申请

US20100013020A1 Semiconductor device with semi-insulating substrate portions 有权
标题翻译：具有半绝缘衬底部分的半导体器件
公开(公告)号：US20100013020A1
公开(公告)日：2010-01-21
申请号：US12586688
申请日：2009-09-24
申请人： Wen-Chin Lin , Denny Tang , Chuan-Ying Lee , H. C. Cheng
发明人： Wen-Chin Lin , Denny Tang , Chuan-Ying Lee , H. C. Cheng
IPC分类号： H01L27/06 , H01L29/06
CPC分类号： H01L21/76 , H01L21/263 , H01L21/26506 , H01L21/266 , H01L21/823481 , H01L21/823878 , H01L27/08
摘要： A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.
摘要翻译：半导体衬底包括在半导体子结构上形成的图案化硬掩模膜的开口下方的半绝缘部分，其厚度足以防止带电粒子通过硬掩模。半绝缘部分包括带电粒子并且可以深深地延伸到半导体衬底中并且电绝缘形成在半绝缘部分的相对侧上的器件。带电粒子可以有利地是质子，并且由图案化的硬掩模膜覆盖的另外的基底部分基本上没有带电粒子。

32. 发明授权

US07622358B2 Semiconductor device with semi-insulating substrate portions and method for forming the same 失效
标题翻译：具有半绝缘基板部分的半导体器件及其形成方法
公开(公告)号：US07622358B2
公开(公告)日：2009-11-24
申请号：US11241574
申请日：2005-09-30
申请人： Wen-Chin Lin , Denny Tang , Chuan-Ying Lee , Hsu Chen Cheng
发明人： Wen-Chin Lin , Denny Tang , Chuan-Ying Lee , Hsu Chen Cheng
IPC分类号： H01L21/76
CPC分类号： H01L21/76 , H01L21/263 , H01L21/26506 , H01L21/266 , H01L21/823481 , H01L21/823878 , H01L27/08
摘要： A method for forming semi-insulating portions in a semiconductor substrate provides depositing a hardmask film over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The hardmask is patterned creating openings through which charged particles pass and enter the substrate during an implantation process. The semi-insulating portions may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.
摘要翻译：在半导体衬底中形成半绝缘部分的方法提供了将半导体衬底上的硬掩模膜沉积到足以防止带电粒子穿过硬掩模的厚度。硬掩模被图案化以产生开孔，在注入过程中带电粒子通过该开口进入衬底。半绝缘部分可以深深地延伸到半导体衬底中并且电绝缘形成在半绝缘部分的相对侧上的器件。带电粒子可以有利地是质子，并且由图案化的硬掩模膜覆盖的另外的基底部分基本上没有带电粒子。

33. 发明申请

US20080186757A1 Advanced MRAM design 有权
标题翻译：先进的MRAM设计
公开(公告)号：US20080186757A1
公开(公告)日：2008-08-07
申请号：US11743453
申请日：2007-05-02
申请人： Wen-Chin Lin , Hsu-Chen Cheng , Yu-Jen Wang , Denny Tang
发明人： Wen-Chin Lin , Hsu-Chen Cheng , Yu-Jen Wang , Denny Tang
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/005 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a technique for created an advanced MRAM array for constructing a memory integrated circuit chip. More specifically, the disclosed principles provide for an integrated circuit memory chip comprised of a combination of at least one of an array of high-speed magnetic memory cells, and at least one of an array of high-density magnetic memory cells. Accordingly, a memory chip constructed as disclosed herein provides the benefit of both high-speed and high-density memory cells on the same memory chip. As a result, applications benefiting from the use of (or perhaps even needing) high-speed memory cells are provided by the memory cells in the high-speed memory cell array.
摘要翻译：这里公开了一种用于创建用于构建存储器集成电路芯片的高级MRAM阵列的技术。更具体地，所公开的原理提供了由高速磁存储器单元的阵列中的至少一个和高密度磁存储单元阵列中的至少一个的组合构成的集成电路存储器芯片。因此，如本文所公开的构造的存储器芯片提供了在相同存储器芯片上的高速和高密度存储器单元的益处。结果，受益于使用（或甚至需要的）高速存储器单元的应用由高速存储单元阵列中的存储单元提供。

34. 发明申请

US20070077697A1 Semiconductor device with semi-insulating substrate portions and method for forming the same 失效
标题翻译：具有半绝缘基板部分的半导体器件及其形成方法
公开(公告)号：US20070077697A1
公开(公告)日：2007-04-05
申请号：US11241574
申请日：2005-09-30
申请人： Wen-Chin Lin , Denny Tang , Chuan-Ying Lee , H. C. Cheng
发明人： Wen-Chin Lin , Denny Tang , Chuan-Ying Lee , H. C. Cheng
IPC分类号： H01L21/8238 , H01L21/425 , H01L21/31
CPC分类号： H01L21/76 , H01L21/263 , H01L21/26506 , H01L21/266 , H01L21/823481 , H01L21/823878 , H01L27/08
摘要： A method for forming semi-insulating portions in a semiconductor substrate provides depositing a hardmask film over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The hardmask is patterned creating openings through which charged particles pass and enter the substrate during an implantation process. The semi-insulating portions may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.
摘要翻译：在半导体衬底中形成半绝缘部分的方法提供了将半导体衬底上的硬掩模膜沉积到足以防止带电粒子穿过硬掩模的厚度。硬掩模被图案化以产生开孔，在注入过程中带电粒子通过该开口进入衬底。半绝缘部分可以深深地延伸到半导体衬底中并且电绝缘形成在半绝缘部分的相对侧上的器件。带电粒子可以有利地是质子，并且由图案化的硬掩模膜覆盖的另外的基底部分基本上没有带电粒子。

35. 发明申请

US20050083747A1 Reference generator for multilevel nonlinear resistivity memory storage elements 失效
标题翻译：多电平非线性电阻率存储元件的参考发生器
公开(公告)号：US20050083747A1
公开(公告)日：2005-04-21
申请号：US10689421
申请日：2003-10-20
申请人： Denny Tang , Wen-Chin Lin
发明人： Denny Tang , Wen-Chin Lin
IPC分类号： G11C5/14 , G11C7/02 , G11C11/16 , G11C11/56
CPC分类号： G11C5/147 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/5607 , G11C2211/5634
摘要： A multilevel reference generator has a plurality of nonlinear standard resistive elements where each resistive element is biased at a constant level to develop a resultant level. The multilevel reference generator has a plurality of mirror sources. Each mirror source is in communication with the one of the plurality of resistive elements such that each mirror source receives the resultant level from the one standard resistive element and provides a mirrored replication of the resultant level. The multilevel reference generator has a plurality of reference level combining circuits. The reference level combining circuit includes a resultant level summing circuit that additively combines the first and second mirrored replication level and a level scaling circuit to create a scaling of the combined first and second mirrored replication levels to create the reference level.
摘要翻译：多电平参考发生器具有多个非线性标准电阻元件，其中每个电阻元件被偏置在恒定电平以产生合成电平。多电平参考发生器具有多个镜源。每个反射镜源与多个电阻元件中的一个电阻元件相通，使得每个反射镜源从一个标准电阻元件接收合成电平，并提供所得电平的镜像复制。多电平参考发生器具有多个参考电平组合电路。参考电平组合电路包括相加地组合第一和第二镜像复制级别的电平求和电路和级别缩放电路，以创建组合的第一和第二镜像复制级别的缩放以创建参考电平。

36. 发明授权

US07719882B2 Advanced MRAM design 有权
标题翻译：先进的MRAM设计
公开(公告)号：US07719882B2
公开(公告)日：2010-05-18
申请号：US11743453
申请日：2007-05-02
申请人： Wen-Chin Lin , Hsu-Chen Cheng , Yu-Jen Wang , Denny Tang
发明人： Wen-Chin Lin , Hsu-Chen Cheng , Yu-Jen Wang , Denny Tang
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/005 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a technique for created an advanced MRAM array for constructing a memory integrated circuit chip. More specifically, the disclosed principles provide for an integrated circuit memory chip comprised of a combination of at least one of an array of high-speed magnetic memory cells, and at least one of an array of high-density magnetic memory cells. Accordingly, a memory chip constructed as disclosed herein provides the benefit of both high-speed and high-density memory cells on the same memory chip. As a result, applications benefiting from the use of (or perhaps even needing) high-speed memory cells are provided by the memory cells in the high-speed memory cell array.
摘要翻译：这里公开了一种用于创建用于构建存储器集成电路芯片的高级MRAM阵列的技术。更具体地，所公开的原理提供了由高速磁存储器单元的阵列中的至少一个和高密度磁存储单元的阵列中的至少一个的组合构成的集成电路存储器芯片。因此，如本文所公开的构造的存储器芯片提供了在相同存储器芯片上的高速和高密度存储器单元的益处。结果，受益于使用（或甚至需要的）高速存储器单元的应用由高速存储单元阵列中的存储单元提供。

37. 发明授权

US07599215B2 Magnetoresistive random access memory device with small-angle toggle write lines 有权
标题翻译：具有小角度切换写入线的磁阻随机存取存储器件
公开(公告)号：US07599215B2
公开(公告)日：2009-10-06
申请号：US11840051
申请日：2007-08-16
申请人： Wen-Chin Lin , Denny Tang , Hsu Chen Cheng
发明人： Wen-Chin Lin , Denny Tang , Hsu Chen Cheng
IPC分类号： G11C11/15
CPC分类号： G11C11/16
摘要： Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired.
摘要翻译：这里公开了具有小角度切换写入线的触发模式磁阻随机存取存储器（MRAM）器件以及触发模式切换MRAM器件的相关方法。还公开了根据所公开的原理构造的MRAM装置的布局。一般来说，所公开的原理提供用于切换切换模式MRAM器件的非正交对准的触发模式写入线，其使用偏置场来降低切换每个器件的磁状态所需的阈值。虽然常规的切换模式写入线提供所施加的磁场的期望的正交取向以优化器件切换，但偏置场的使用影响该正交取向。如本文所公开的，通过非正交对准这两个写入线，可以补偿偏置场的有害影响，使得如所期望的那样，施加到两条线的器件的净场也基本正交。

38. 发明申请

US20080239794A1 Magnetoresistive random access memory device with small-angle toggle write lines 有权
标题翻译：具有小角度切换写入线的磁阻随机存取存储器件
公开(公告)号：US20080239794A1
公开(公告)日：2008-10-02
申请号：US11840051
申请日：2007-08-16
申请人： Wen-Chin Lin , Denny Tang , Hsu-Chen Cheng
发明人： Wen-Chin Lin , Denny Tang , Hsu-Chen Cheng
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired.
摘要翻译：这里公开了具有小角度切换写入线的触发模式磁阻随机存取存储器（MRAM）器件以及触发模式切换MRAM器件的相关方法。还公开了根据所公开的原理构造的MRAM装置的布局。一般来说，所公开的原理提供用于切换切换模式MRAM器件的非正交对准的触发模式写入线，其使用偏置场来降低切换每个器件的磁状态所需的阈值。虽然常规的切换模式写入线提供所施加的磁场的期望的正交取向以优化器件切换，但偏置场的使用影响该正交取向。如本文所公开的，通过非正交对准这两个写入线，可以补偿偏置场的有害影响，使得如所期望的那样，施加到两条线的器件的净场也基本正交。

39. 发明授权

US07349243B2 3-parameter switching technique for use in MRAM memory arrays 有权
标题翻译：用于MRAM存储器阵列的3参数切换技术
公开(公告)号：US07349243B2
公开(公告)日：2008-03-25
申请号：US11379527
申请日：2006-04-20
申请人： Wen-Chin Lin , Denny Tang , Hsu-Chen Cheng
发明人： Wen-Chin Lin , Denny Tang , Hsu-Chen Cheng
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： Disclosed herein are various embodiments of a 3-parameter switching technique for MRAM memory cells arranged on an MRAM array. The disclosed technique alters the relationship between the disturbance margin and write margin of MRAM arrays to reduce the overall disturbance for the arrays by either enlarging the write margin with respect to the original disturbance margin or enlarging the disturbance margin in view of the original write margin. In either approach, the disclosed 3-parameter switching technique successfully decreases the inadvertent writing of unselected bits.
摘要翻译：这里公开了布置在MRAM阵列上的MRAM存储器单元的3参数切换技术的各种实施例。所公开的技术改变MRAM阵列的扰动余量与写入余量之间的关系，以通过相对于原始干扰裕度放大写入裕度或者根据原始写入裕度来扩大扰动余量来减小阵列的整体干扰。在任一方法中，所公开的3参数切换技术成功地减少了无选择位的无意写入。

40. 发明申请

US20070247900A1 3-parameter switching technique for use in MRAM memory arrays 有权
标题翻译：用于MRAM存储器阵列的3参数切换技术
公开(公告)号：US20070247900A1
公开(公告)日：2007-10-25
申请号：US11379527
申请日：2006-04-20
申请人： Wen-Chin Lin , Denny Tang , H.C. Cheng
发明人： Wen-Chin Lin , Denny Tang , H.C. Cheng
IPC分类号： G11C11/14
CPC分类号： G11C11/16
摘要： Disclosed herein are various embodiments of a 3-parameter switching technique for MRAM memory cells arranged on an MRAM array. The disclosed technique alters the relationship between the disturbance margin and write margin of MRAM arrays to reduce the overall disturbance for the arrays by either enlarging the write margin with respect to the original disturbance margin or enlarging the disturbance margin in view of the original write margin. In either approach, the disclosed 3-parameter switching technique successfully decreases the inadvertent writing of unselected bits.
摘要翻译：这里公开了布置在MRAM阵列上的MRAM存储器单元的3参数切换技术的各种实施例。所公开的技术改变MRAM阵列的扰动余量与写入余量之间的关系，以通过相对于原始干扰裕度放大写入裕度或者根据原始写入裕度来扩大扰动余量来减小阵列的整体干扰。在任一方法中，所公开的3参数切换技术成功地减少了无选择位的无意写入。

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