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31. 发明授权

US07087526B1 Method of fabricating a p-type CaO-doped SrCu2O2 thin film 有权
标题翻译：制造p型CaO掺杂SrCu2O2薄膜的方法
公开(公告)号：US07087526B1
公开(公告)日：2006-08-08
申请号：US11261020
申请日：2005-10-27
申请人： Wei-Wei Zhuang , Wei Gao , Yoshi Ono
发明人： Wei-Wei Zhuang , Wei Gao , Yoshi Ono
IPC分类号： H01L23/02
CPC分类号： C23C26/00
摘要： A method of CaO-doped SrCu2O2 spin-on precursor synthesis and low temperature p-type thin film deposition, includes preparing a wafer to receive a spin-coating thereon; selecting metalorganic compounds to form a SrCu2O2 precursor, mixing and refluxing the metalorganic compounds to form a precursor mixture; filtering the precursor mixture to produce a spin-coating precursor; applying the spin-coating precursor to the wafer in a two-step spin coating procedure; baking the spin-coated wafer using a hot-plate bake to evaporate substantially all of the solvents; and annealing the spin-coated wafer to form a CaO-doped SrCu2O2 layer thereon.
摘要翻译：掺有CaO的SrCu 2 O 2 O 2旋涂前体合成和低温p型薄膜沉积的方法包括制备晶片以在其上接受旋涂法 ; 选择金属有机化合物以形成SrCu 2 O 2 O 2前体，将金属有机化合物混合并回流以形成前体混合物; 过滤前体混合物以产生旋涂前体; 以两步旋涂方法将旋涂前驱体施加到晶片上; 使用热板烘烤烘烤旋涂的晶片以基本上蒸发所有溶剂; 以及对旋涂的晶片退火以在其上形成掺杂CaO的SrCu 2 O 2 O 2层。

32. 发明授权

US06873048B2 System and method for integrating multiple metal gates for CMOS applications 失效
标题翻译：用于集成多个金属栅极用于CMOS应用的系统和方法
公开(公告)号：US06873048B2
公开(公告)日：2005-03-29
申请号：US10376795
申请日：2003-02-27
申请人： Wei Gao , John F. Conley, Jr. , Yoshi Ono
发明人： Wei Gao , John F. Conley, Jr. , Yoshi Ono
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78 , H01L23/48
CPC分类号： H01L29/66583 , H01L21/823842 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A dual-gate MOSFET with metal gates and a method for setting threshold voltage in such a MOSFET is provided. The method comprises: forming a gate oxide layer overlying first and second channel regions; forming a first metal layer having a first thickness overlying the gate oxide layer; forming a second metal layer having a second thickness overlying the first metal layer first thickness; selectively removing the second metal layer overlying the first channel region; forming a third metal layer; establishing a first MOSFET with a gate work function responsive to the thicknesses of the first and third metal layer overlying the first channel region; and, establishing a second MOSFET, complementary to the first MOSFET, with a gate work function responsive to the combination of the thicknesses of the first, second, and third metal layers overlying the second channel region.
摘要翻译：提供了具有金属栅极的双栅极MOSFET和用于设置这种MOSFET中的阈值电压的方法。该方法包括：形成覆盖第一和第二沟道区的栅极氧化层; 形成具有覆盖所述栅极氧化物层的第一厚度的第一金属层; 形成具有覆盖所述第一金属层第一厚度的第二厚度的第二金属层; 选择性地去除覆盖在第一沟道区上的第二金属层; 形成第三金属层; 建立具有响应于覆盖在第一沟道区上的第一和第三金属层的厚度的栅极功函数的第一MOSFET; 以及响应于覆盖在第二沟道区上的第一，第二和第三金属层的厚度的组合，建立与第一MOSFET互补的第二MOSFET。

33. 发明授权

US06825106B1 Method of depositing a conductive niobium monoxide film for MOSFET gates 失效
标题翻译：沉积用于MOSFET栅极的导电铌氧化物膜的方法
公开(公告)号：US06825106B1
公开(公告)日：2004-11-30
申请号：US10676987
申请日：2003-09-30
申请人： Wei Gao , Yoshi Ono
发明人： Wei Gao , Yoshi Ono
IPC分类号： H01L213205
CPC分类号： H01L29/66545 , H01L21/28088 , H01L29/78
摘要： A method is provided to deposit niobium monoxide gates. An elemental metal target, or a composite niobium monoxide target is provided within a sputtering chamber. A substrate with gate dielectric, for example silicon dioxide or a high-k gate dielectric, is provided in the sputtering chamber. The sputtering power and oxygen partial pressure within the chamber is set to deposit a film comprising niobium monoxide, without excess amounts of elemental niobium, NbO2 insulator, or Nb2O5 insulator. The deposition method may be incorporated into a standard CMOS fabrication process, or a replacement gate CMOS process.
摘要翻译：提供了一种沉积一氧化monoxide栅的方法。在溅射室内设置元素金属靶或复合铌靶。在溅射室中提供具有栅极电介质的衬底，例如二氧化硅或高k栅极电介质。室内的溅射功率和氧分压被设定为沉积包含一氧化铌的膜，而不含过量的元素铌，NbO 2绝缘体或Nb 2 O 5绝缘体。沉积方法可以结合到标准CMOS制造工艺或替代栅极CMOS工艺中。

34. 发明授权

US07678512B2 Method of making a grayscale reticle using step-over lithography for shaping microlenses 失效
标题翻译：使用逐步光刻制作灰阶标线的方法，用于成型微透镜
公开(公告)号：US07678512B2
公开(公告)日：2010-03-16
申请号：US11657326
申请日：2007-01-24
申请人： Yoshi Ono , Bruce D. Ulrich , Wei Gao
发明人： Yoshi Ono , Bruce D. Ulrich , Wei Gao
IPC分类号： G03F1/00
CPC分类号： G03F7/0005 , G03F1/50
摘要： A method of fabricating a grayscale reticle includes preparing a quartz wafer substrate; depositing a layer of SRO on the top surface of the quartz substrate; patterning and etching the SRO to form an initial microlens pattern using step-over lithography; patterning and etching the SRO to form a recessed pattern in the SRO; depositing an opaque film on the SRO; patterning and etching the opaque film; depositing and planarizing a planarizing layer; cutting the quartz wafer into rectangular pieces sized to be smaller than a selected blank reticle; bonding the a piece a to selected reticle blank to form a grayscale reticle; and using the grayscale reticle to form a microlens array on a photoimager.
摘要翻译：制造灰度标线的方法包括制备石英晶片衬底; 在石英衬底的顶表面上沉积SRO层; 图案化和蚀刻SRO以使用逐步光刻形成初始微透镜图案; 图案化和蚀刻SRO以在SRO中形成凹陷图案; 在SRO上沉积不透明膜; 图案化和蚀刻不透明膜; 沉积和平坦化平坦化层; 将石英晶片切割成尺寸小于所选空白掩模版的矩形块; 将片a粘合到所选的掩模版坯料上以形成灰度标线; 并使用灰度标线在光学成像仪上形成微透镜阵列。

35. 发明授权

US07473640B2 Reactive gate electrode conductive barrier 有权
标题翻译：无源栅电极导电屏障
公开(公告)号：US07473640B2
公开(公告)日：2009-01-06
申请号：US10784662
申请日：2004-02-23
申请人： John F. Conley, Jr. , Yoshi Ono , Wei Gao
发明人： John F. Conley, Jr. , Yoshi Ono , Wei Gao
IPC分类号： H01L29/72
CPC分类号： H01L21/28079 , H01L21/823842 , H01L29/4958
摘要： A method, and corresponding transistor structure are provided for protecting the gate electrode from an underlying gate insulator. The method comprises: forming a gate insulator overlying a channel region; forming a first metal barrier overlying the gate insulator, having a thickness of less than 5 nanometers (nm); forming a second metal gate electrode overlying the first metal barrier, having a thickness of greater than 10 nm; and, establishing a gate electrode work function exclusively responsive to the second metal. The second metal gate electrode can be one of the following materials: elementary metals such as p+ poly, n+ poly. Ta, W, Re, RuO2, Pt, Ti, Hf, Zr, Cu, V, Ir, Ni, Mn, Co, NbO, Pd, Mo, TaSiN, and Nb, and binary metals such as WN, TaN, and TiN. The first metal barrier can be a binary metal, such as TaN, TiN, or WN.
摘要翻译：提供了一种方法和相应的晶体管结构，用于保护栅极免受下层栅极绝缘体的影响。该方法包括：形成覆盖沟道区的栅极绝缘体; 形成覆盖栅极绝缘体的厚度小于5纳米（nm）的第一金属屏障; 形成覆盖所述第一金属屏障的第二金属栅电极，其厚度大于10nm; 并且建立专门响应于第二金属的栅电极功函数。第二金属栅电极可以是以下材料之一：元素金属，例如p + poly，n + poly。 Ta，W，Re，RuO 2，Pt，Ti，Hf，Zr，Cu，V，Ir，Ni，Mn，Co，NbO，Pd，Mo，TaSiN和Nb，二元金属如WN，TaN和TiN 。第一金属屏障可以是二元金属，例如TaN，TiN或WN。

36. 发明申请

US20080197107A1 Method of fabricating a grayscale mask using a wafer bonding process 失效
标题翻译：使用晶片接合工艺制造灰度掩模的方法
公开(公告)号：US20080197107A1
公开(公告)日：2008-08-21
申请号：US11709008
申请日：2007-02-20
申请人： Wei Gao , Bruce D. Ulrich , Yoshi Ono
发明人： Wei Gao , Bruce D. Ulrich , Yoshi Ono
IPC分类号： C25F3/00
CPC分类号： G03F1/68 , G03F1/50 , G03F1/54
摘要： A method of fabricating a grayscale mask includes preparing a quartz wafer; depositing a layer of Si3N4 on the quartz wafer; depositing a layer of titanium/TEOS directly on the Si3N4 layer on the backside of the quartz wafer; removing the layer of Si3N4 from the front side of the quartz wafer; depositing a layer of SRO directly on the front side of the quartz wafer; patterning a microlens array on the SRO layer; etching the SRO layer to form a microlens array in the SRO layer; depositing a layer of titanium; patterning and etching the titanium layer; depositing a layer of SiOxNy on the SRO microlens array; CMP to planarize the layer of SiOxNy removing the titanium/TEOS layer from the backside of the quartz wafer; bonding the planarized SiOxNy to a quartz reticle plate; and etching to remove Si3N4 from the bonded structure to form a grayscale mask reticle.
摘要翻译：制造灰度掩模的方法包括制备石英晶片; 在石英晶片上沉积一层Si 3 N 4 N 4; 在石英晶片的背面上的Si 3 N 4 N 4层上直接沉积钛/ TEOS层; 从石英晶片的正面去除Si 3 N 4 N 4层; 在石英晶片的正面上直接沉积SRO层; 在SRO层上构图微透镜阵列; 蚀刻SRO层以在SRO层中形成微透镜阵列; 沉积一层钛; 图案化和蚀刻钛层; 在SRO微透镜阵列上沉积一层SiO 2 x N y O; CMP以平坦化从石英晶片的背面去除钛/ TEOS层的SiO 2 x N y层; 将平坦化的SiO x N N y N键合到石英光罩板上; 以及蚀刻以从结合结构去除Si 3 N 4 N 4以形成灰度掩模掩模版。

37. 发明申请

US20080176148A1 Method of making a grayscale reticle using step-over lithography for shaping microlenses 失效
标题翻译：使用逐步光刻制作灰阶标线的方法，用于成型微透镜
公开(公告)号：US20080176148A1
公开(公告)日：2008-07-24
申请号：US11657326
申请日：2007-01-24
申请人： Yoshi Ono , Bruce D. Ulrich , Wei Gao
发明人： Yoshi Ono , Bruce D. Ulrich , Wei Gao
IPC分类号： G03F1/00
CPC分类号： G03F7/0005 , G03F1/50
摘要： A method of fabricating a grayscale reticle includes preparing a quartz wafer substrate; depositing a layer of SRO on the top surface of the quartz substrate; patterning and etching the SRO to form an initial microlens pattern using step-over lithography; patterning and etching the SRO to form a recessed pattern in the SRO; depositing an opaque film on the SRO; patterning and etching the opaque film; depositing and planarizing a planarizing layer; cutting the quartz wafer into rectangular pieces sized to be smaller than a selected blank reticle; bonding the a piece a to selected reticle blank to form a grayscale reticle; and using the grayscale reticle to form a microlens array on a photoimager.
摘要翻译：制造灰度标线的方法包括制备石英晶片衬底; 在石英衬底的顶表面上沉积SRO层; 图案化和蚀刻SRO以使用逐步光刻形成初始微透镜图案; 图案化和蚀刻SRO以在SRO中形成凹陷图案; 在SRO上沉积不透明膜; 图案化和蚀刻不透明膜; 沉积和平坦化平坦化层; 将石英晶片切割成尺寸小于所选空白掩模版的矩形块; 将片a粘合到所选的掩模版坯料上以形成灰度标线; 并使用灰度标线在光学成像仪上形成微透镜阵列。

38. 发明申请

US20070054042A1 Method of SrCu2O2 spin-on precursor synthesis and low temperature p-type thin film deposition 审中-公开
标题翻译： SrCu2O2旋涂前驱体合成方法及低温p型薄膜沉积方法
公开(公告)号：US20070054042A1
公开(公告)日：2007-03-08
申请号：US11220885
申请日：2005-09-06
申请人： Wei-Wei Zhuang , Yoshi Ono , Wei Gao
发明人： Wei-Wei Zhuang , Yoshi Ono , Wei Gao
IPC分类号： B05D3/12 , B05D3/02
CPC分类号： C01G3/00 , C01P2002/72 , H01L21/02381 , H01L21/02403 , H01L21/02472 , H01L21/02565 , H01L21/02579 , H01L21/02628
摘要： A method of SrCu2O2 spin-on precursor synthesis and low temperature p-type thin film deposition, includes preparing a wafer to receive a spin-coating thereon; selecting metalorganic compounds to form a SrCu2O2 precursor, mixing and refluxing the metalorganic compounds to form a precursor mixture; filtering the precursor mixture to produce a spin-coating precursor; applying the spin-coating precursor to the wafer in a two-step spin coating procedure; baking the spin-coated wafer using a hot-plate bake to evaporate substantially all of the solvents; and annealing the spin-coated wafer to form a SrCu2O2 layer thereon in a two-step post-anneal process.
摘要翻译： SrCu 2 O 2 O 2旋转前体合成和低温p型薄膜沉积的方法包括制备晶片以在其上接受旋涂; 选择金属有机化合物以形成SrCu 2 O 2 O 2前体，将金属有机化合物混合并回流以形成前体混合物; 过滤前体混合物以产生旋涂前体; 以两步旋涂方法将旋涂前驱体施加到晶片上; 使用热板烘烤烘烤旋涂的晶片以基本上蒸发所有溶剂; 并在两步后退火工艺中退火旋涂晶片以形成SrCu 2 O 2 O 2层。

39. 发明申请

US20060250072A1 Zinc oxide N-I-N electroluminescence device 失效
公开(公告)号：US20060250072A1
公开(公告)日：2006-11-09
申请号：US11123603
申请日：2005-05-06
申请人： Sheng Hsu , Yoshi Ono
发明人： Sheng Hsu , Yoshi Ono
IPC分类号： H01J1/62 , H01J63/04
CPC分类号： H01L33/0004 , H01L33/26
摘要： A method is provided for forming a ZnO Si N—I—N EL device. The method comprises: forming an n-doped Si layer; forming a Si oxide (SiO2) layer overlying the n-doped Si layer; forming an n-type ZnO layer overlying the SiO2 layer; and, forming an electrode overlying the ZnO layer. The electrode can be a transparent material such as indium tin oxide, zinc oxyfluoride, or a conductive plastic. The n-doped Si layer can be polycrystalline or single-crystal Si. In some aspects, the Si oxide layer has a thickness in the range of 1 to 20 nm. More preferably, the thickness is 2 to 5 nm. The ZnO layer thickness is in the range of 10 to 200 nm.

40. 发明授权

US07208768B2 Electroluminescent device 失效
标题翻译：电致发光器件
公开(公告)号：US07208768B2
公开(公告)日：2007-04-24
申请号：US10836669
申请日：2004-04-30
申请人： Yoshi Ono , Wei Gao , John F. Conley, Jr. , Osamu Nishio , Keizo Sakiyama
发明人： Yoshi Ono , Wei Gao , John F. Conley, Jr. , Osamu Nishio , Keizo Sakiyama
IPC分类号： H01L27/15
CPC分类号： H01L33/28 , H01L33/18 , H01L33/34 , Y10S977/95
摘要： A method is provided for forming an electroluminescent device. The method comprises: providing a type IV semiconductor material substrate; forming a p+/n+ junction in the substrate, typically a plurality of interleaved p+/n+ junctions are formed; and, forming an electroluminescent layer overlying the p+/n+ junction(s) in the substrate. The type IV semiconductor material substrate can be Si, C, Ge, SiGe, or SiC. For example, the substrate can be Si on insulator (SOI), bulk Si, Si on glass, or Si on plastic. The electroluminescent layer can be a material such as nanocrystalline Si, nanocrystalline Ge, fluorescent polymers, or type II–VI materials such as ZnO, ZnS, ZnSe, CdSe, and CdS. In some aspect, the method further comprises forming an insulator film interposed between the substrate and the electroluminescent layer. In another aspect, the method comprises forming a conductive electrode overlying the electroluminescent layer.
摘要翻译：提供了形成电致发光器件的方法。该方法包括：提供IV型半导体材料基板; 在衬底中形成p + / n +结，通常形成多个交错的p + / n +结; 并且形成覆盖衬底中的p + / n +结的电致发光层。 IV型半导体材料基板可以是Si，C，Ge，SiGe或SiC。例如，衬底可以是绝缘体上的硅（SOI），玻璃上的体积Si，Si或塑料上的Si。电致发光层可以是诸如纳米晶体Si，纳米晶体Ge，荧光聚合物或诸如ZnO，ZnS，ZnSe，CdSe和CdS的II-VI族材料的材料。在一些方面，所述方法还包括形成介于基片和电致发光层之间的绝缘膜。另一方面，该方法包括形成覆盖电致发光层的导电电极。

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