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31. 发明申请

US20080067608A1 Storage Elements with Disguised Configurations and Methods of Using the Same 审中-公开
标题翻译：具有伪装配置的存储元件及其使用方法
公开(公告)号：US20080067608A1
公开(公告)日：2008-03-20
申请号：US11928663
申请日：2007-10-30
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L27/06
CPC分类号： H01L23/585 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a gate region of the MOSFET; and (3) an implanted region coupled to the source/drain diffusion regions of the MOSFET such that a path between the source/drain diffusion regions functions as a short circuit or an open circuit. In another aspect, a design structure embodied in a machine readable medium for designing manufacturing, or testing a design is provided. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是具有（1）具有源极/漏极扩散区域的金属氧化物半导体场效应晶体管（MOSFET）的集成电路（IC）的元件; （2）耦合到所述MOSFET的电熔丝（eFuse），使得所述eFuse的一部分用作所述MOSFET的栅极区域; 和（3）耦合到MOSFET的源极/漏极扩散区域的注入区域，使得源极/漏极扩散区域之间的路径用作短路或开路。在另一方面，提供了体现在用于设计制造的机器可读介质或测试设计中的设计结构。提供了许多其他方面。

32. 发明申请

US20080057671A1 SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION AND METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES 有权
标题翻译：用于锁定抑制的半导体结构和形成这种半导体结构的方法
公开(公告)号：US20080057671A1
公开(公告)日：2008-03-06
申请号：US11927135
申请日：2007-10-29
申请人： Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
发明人： Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
IPC分类号： H01L21/762
CPC分类号： H01L21/76237 , H01L21/26533 , H01L21/76213 , H01L21/76229 , H01L21/76232 , H01L21/823878 , H01L27/0921 , H01L29/1087 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。该半导体结构包括成形修饰的隔离区，其形成在通常在制造本体CMOS器件的衬底的两个掺杂阱之间的沟槽中。成形改进的隔离区域可以包括沟槽的加宽的电介质填充部分，其可以可选地包括分隔两个掺杂阱之间的损伤区域的沟槽的附近损伤区域或狭窄的电介质填充部分。也可以通过在沟槽中的沟槽基底和介电填料之间提供晶格不匹配的层来抑制闩锁。

33. 发明申请

US20080048265A1 SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES 有权
公开(公告)号：US20080048265A1
公开(公告)日：2008-02-28
申请号：US11927110
申请日：2007-10-29
申请人： Roger Booth , Jack Mandelman , William Tonti
发明人： Roger Booth , Jack Mandelman , William Tonti
IPC分类号： H01L27/12
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

34. 发明申请

US20070210412A1 ELECTRICALLY PROGRAMMABLE PI-SHAPED FUSE STRUCTURES AND METHODS OF FABRICATION THEREOF 有权
标题翻译：电气可编程PI形状的保险丝结构及其制造方法
公开(公告)号：US20070210412A1
公开(公告)日：2007-09-13
申请号：US11372380
申请日：2006-03-09
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.
摘要翻译：提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。

35. 发明申请

US20070182030A1 High-voltage silicon-on-insulator transistors and methods of manufacturing the same 失效
标题翻译：高压硅绝缘体晶体管及其制造方法
公开(公告)号：US20070182030A1
公开(公告)日：2007-08-09
申请号：US11347413
申请日：2006-02-03
申请人： William Ma , Jack Mandelman , Carl Radens , William Tonti
发明人： William Ma , Jack Mandelman , Carl Radens , William Tonti
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/66772 , H01L29/78612 , H01L29/78624 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了制造高压晶体管的第一种方法。第一种方法包括以下步骤：（1）提供包括在绝缘体上硅（SOI）层之下的绝缘体层下面的体硅层的衬底; 以及（2）形成包括SOI层中的晶体管的扩散区域的晶体管节点的一个或多个部分。晶体管节点的一部分适于将晶体管内的大于约5V的电压减小到小于约3V的电压。提供了许多其它方面。

36. 发明申请

US20070120218A1 CMOS compatible shallow-trench efuse structure and method 失效
标题翻译： CMOS兼容浅沟槽结构和方法
公开(公告)号：US20070120218A1
公开(公告)日：2007-05-31
申请号：US11290890
申请日：2005-11-30
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L21/268 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention also provides a method of fabricating such a semiconductor structure in which the embedded e-fuse is formed substantially at the same time with the trench isolation regions.
摘要翻译：提供了包括位于半导体衬底（主体或绝缘体中半导体）的沟槽内的至少一个电子熔丝的半导体结构。根据本发明，电熔丝与位于半导体衬底内的掺杂区电接触。本发明还提供一种制造这种半导体结构的方法，其中嵌入式电熔丝基本上与沟槽隔离区域同时形成。

37. 发明申请

US20080052659A1 Electrically Programmable pi-Shaped Fuse Structures and Design Process Therefore 失效
标题翻译：电可编程的pi形保险丝结构和设计过程
公开(公告)号：US20080052659A1
公开(公告)日：2008-02-28
申请号：US11923833
申请日：2007-10-25
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： G06F17/50
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void. The design structure for the fuse is embodied in a machine-readable medium for designing, manufacturing or testing a design of the fuse.
摘要翻译：提出了用于集成电路的电可编程保险丝及其设计结构，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙之上。保险丝的设计结构体现在用于设计，制造或测试保险丝设计的机器可读介质中。

38. 发明申请

US20070247273A1 ELECTRICALLY PROGRAMMABLE PI-SHAPED FUSE STRUCTURES AND METHODS OF FABRICATION THEREOF 失效
公开(公告)号：US20070247273A1
公开(公告)日：2007-10-25
申请号：US11768254
申请日：2007-06-26
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： H01H85/06 , H01L21/336 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.

39. 发明申请

US20070210890A1 Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
标题翻译：具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上
公开(公告)号：US20070210890A1
公开(公告)日：2007-09-13
申请号：US11372387
申请日：2006-03-09
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01H85/04
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

40. 发明申请

US20070170543A1 Methods and semiconductor structures for latch-up suppression using a conductive region 失效
标题翻译：使用导电区域进行闩锁抑制的方法和半导体结构
公开(公告)号：US20070170543A1
公开(公告)日：2007-07-26
申请号：US11340752
申请日：2006-01-26
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Jack Mandelman , William Tonti
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Jack Mandelman , William Tonti
IPC分类号： H01L29/00
CPC分类号： H01L27/0921 , H01L21/823878 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。半导体结构包括形成在衬底的半导体材料中的第一和第二相邻的掺杂阱。在第一和第二掺杂阱之间的衬底中限定了包括基底和基底与顶表面之间的第一侧壁的沟槽。沟槽部分地填充有与第一和第二掺杂阱电耦合的导体材料。可以在与沟槽中的导电材料相邻的位置处与沟槽邻接的半导体材料中提供高度掺杂的导电区域。

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