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31. 发明申请

US20080148024A1 Hardware Accelerator 有权
标题翻译：硬件加速器
公开(公告)号：US20080148024A1
公开(公告)日：2008-06-19
申请号：US11610871
申请日：2006-12-14
申请人： Gilbert M. Wolrich , William Hasenplaugh , Wajdi Feghali , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Gilbert M. Wolrich , William Hasenplaugh , Wajdi Feghali , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F9/302
CPC分类号： G06F9/30014 , G06F21/72
摘要： The present disclosure provides a method for instruction processing. The method may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit. The method may further include loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand. The method may also include performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register. The method may further include loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand. The method may additionally include generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于指令处理的方法。该方法可以包括从第一寄存器，第二操作数，第二寄存器和进位输入位添加第一操作数，以产生和和执行位。该方法还可以包括将和加载到第三寄存器中，并且将进位位加载到第三寄存器的最高有效位位置以产生第三操作数。该方法还可以包括经由移位器单元在第三操作数上执行单位移位以产生移位的操作数，并将移位的操作数加载到第四寄存器中。该方法还可以包括将最小有效位加载到第四寄存器的最高有效位位置以产生第四操作数。该方法可以另外包括经由第四操作数生成第一和第二操作数的最大公约数（GCD），并且至少部分地基于GCD生成公钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

32. 发明申请

US20080140753A1 Multiplier 审中-公开
标题翻译：乘数
公开(公告)号：US20080140753A1
公开(公告)日：2008-06-12
申请号：US11636016
申请日：2006-12-08
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi Feghali , Robert P. Ottavi
发明人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi Feghali , Robert P. Ottavi
IPC分类号： G06F17/00
CPC分类号： G06F7/5324
摘要： An electronically implemented method includes multiplying a number A, and a number B, where A is composed of segments ai and B is composed of segments bj where i and j are integers greater than 1. The multiplying includes determining partial product values for at least some of aibj and determining a sum of partial product values for aibj and ajbi where ai=bj and bj=ai for respective values of i and j, by multiplying one of (1) aibj and (2) ajbi by two. A sum is determined and stored in a memory storage element of the determined partial product values and the determined sum of partial product values for aibj and ajbi.
摘要翻译：电子实现的方法包括将数字A和数字B相乘，其中A由段α1和B组成，并且B由分段b和j分别组成，其中i和j是大于1的整数。乘法包括确定对于第一个子集的至少一些的部分乘积值，并且确定第一个子集的部分乘积值的和， / SUB＆gt; j＆lt; i＆gt;和＆lt; i＆lt; i＆lt; i＆lt; i＆lt; i＆lt; 并且对于i和j的各个值，通过将（1）a个子集合中的一个来代替，并且对于i和j的各个值，b＆lt; i＆lt; i＆lt; 和（2）第二个和第二个。确定和并将其存储在所确定的部分乘积值的存储器存储元件中，并且将所确定的部分乘积值的总和存储到第一和第二 b

33. 发明申请

US20190236022A1 ULTRA-SECURE ACCELERATORS 审中-公开
公开(公告)号：US20190236022A1
公开(公告)日：2019-08-01
申请号：US16377230
申请日：2019-04-07
申请人： Vinodh Gopal , Wajdi Feghali , Raghunandan Makaram
发明人： Vinodh Gopal , Wajdi Feghali , Raghunandan Makaram
IPC分类号： G06F12/109 , G06F3/06
CPC分类号： G06F12/109 , G06F3/0622 , G06F3/0659 , G06F3/0673
摘要： Methods and apparatus for ultra-secure accelerators. New ISA enqueue (ENQ) instructions with a wrapping key (WK) are provided to facilitate secure access to on-chip and off-chip accelerators in computer platforms and systems. The ISA ENQ with WK instructions include a dest operand having an address of an accelerator portal and a scr operand having the address of a request descriptor in system memory defining a job to be performed by an accelerator and including a wrapped key. Execution of the instruction writes a record including the src and a WK to the portal, and the record is enqueued in an accelerator queue if a slot is available. The accelerator reads the enqueued request descriptor and uses the WK to unwrap the wrapped key, which is then used to decrypt encrypted data read from one or more buffers in memory. The accelerator then performs one or more functions on the decrypted data as defined by the job and writes the output of the processing back to memory with optional encryption.

34. 发明申请

US20190042496A1 DELAYED LINK COMPRESSION SCHEME 审中-公开
公开(公告)号：US20190042496A1
公开(公告)日：2019-02-07
申请号：US16140472
申请日：2018-09-24
申请人： Simon N. Peffers , Kirk S. Yap , Sean Gulley , Vinodh Gopal , Wajdi Feghali
发明人： Simon N. Peffers , Kirk S. Yap , Sean Gulley , Vinodh Gopal , Wajdi Feghali
IPC分类号： G06F13/16 , H04L29/06 , G06F13/28 , G06F13/40
摘要： Apparatus, systems and methods for implementing delayed decompression schemes. As a burst of packets comprising compressed packets and uncompressed packets are received over an interconnect link, they are buffered in a receive buffer without decompression. Subsequently, the packets are forwarded from the receive buffer to a consumer such as processor core, with the compressed packets being decompressed prior to reaching the processor core. Under a first delayed decompression approach, packets are decompressed when they are read from the receive buffer in conjunction with forwarding the uncompressed packet (or uncompressed data contained therein) to the consumer. Under a second delayed decompression scheme, the packets are read from the receive buffer and forwarded to a decompressor using a first datapath width matching the width of the packets, decompressed, and then forwarded to the consumer using a second datapath width matching the width of the uncompressed data.

35. 发明申请

US20110264720A1 CRYPTOGRAPHIC SYSTEM, METHOD AND MULTIPLIER 有权
标题翻译： CRYPTOGRAPHIC系统，方法和乘法器
公开(公告)号：US20110264720A1
公开(公告)日：2011-10-27
申请号：US11323994
申请日：2005-12-30
申请人： Wajdi Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F7/52 , G06F5/01
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译：通常，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的组具有访问第一操作数和第二操作数以乘以具有多个段的第一操作数和第二操作数具有多个段的操作数。所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的相应一个，直到所述第二操作数已被提供给第一个操作数的每个段。该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器中的不同乘法器的输出。乘法器还包括耦合到逻辑的累加器。

36. 发明授权

US08020142B2 Hardware accelerator 有权
标题翻译：硬件加速器
公开(公告)号：US08020142B2
公开(公告)日：2011-09-13
申请号：US11610871
申请日：2006-12-14
申请人： Gilbert M. Wolrich , William Hasenplaugh , Wajdi Feghali , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Gilbert M. Wolrich , William Hasenplaugh , Wajdi Feghali , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F9/44 , G06F9/45 , G06F7/38
CPC分类号： G06F9/30014 , G06F21/72
摘要： A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit, loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand, performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register, loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand, generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Many alternatives, variations and modifications are possible.
摘要翻译：一种用于指令处理的方法可以包括从第一寄存器，第二操作数，第二寄存器和进位输入位添加第一操作数，以产生和和执行位，将所述和加载到第三寄存器并加载进位位到第三寄存器的最高有效位位置以产生第三操作数，经由移位器单元在第三操作数上执行单位移位以产生移位操作数，并将移位的操作数加载到第四寄存器中，加载最低有效位从总和到第四寄存器的最高有效位位置以产生第四操作数，经由第四操作数产生第一和第二操作数的最大公约数（GCD），并且至少部分地基于第二操作数生成公钥， GCD。许多替代方案，变化和修改是可能的。

37. 发明授权

US07912886B2 Configurable exponent FIFO 有权
标题翻译：可配置指数FIFO
公开(公告)号：US07912886B2
公开(公告)日：2011-03-22
申请号：US11610841
申请日：2006-12-14
申请人： Vinodh Gopal , Wajdi Feghali , Gilbert M. Wolrich , Daniel Cutter , Robert P. Ottavi
发明人： Vinodh Gopal , Wajdi Feghali , Gilbert M. Wolrich , Daniel Cutter , Robert P. Ottavi
IPC分类号： G06F7/38 , H04K1/00 , H04L9/00 , H04L9/30
CPC分类号： G06F7/723
摘要： The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的系统和方法。该方法包括将来自存储器的向量的第一字加载到第一寄存器中，并随后将第一个字从第一寄存器加载到第二寄存器。该方法还可以包括将第二字加载到第一寄存器中并将至少一个比特从第二寄存器加载到算术逻辑单元中。该方法还可以包括在至少一个比特上执行模幂运算以产生结果，并且至少部分地基于结果生成公开密钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

38. 发明授权

US07797612B2 Storage accelerator 有权
标题翻译：存储加速器
公开(公告)号：US07797612B2
公开(公告)日：2010-09-14
申请号：US11617966
申请日：2006-12-29
申请人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
发明人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
IPC分类号： G11C29/00
CPC分类号： G06F11/1076 , G06F2211/1057
摘要： The present disclosure provides a method for generating RAID syndromes. In one embodiment the method may include loading a first data byte of a first disk block and a first data byte of a second disk block from a storage device to an arithmetic logic unit. The method may further include XORing the first data byte of the first disk block and the first data byte of the second disk block to generate a first result and storing the first result in a results buffer. The method may also include iteratively repeating, loading intermediate data bytes corresponding to the first disk block and intermediate data bytes corresponding to the second disk block from the storage device to the arithmetic logic unit. The method may additionally include XORing the intermediate data bytes corresponding to the first disk block and the intermediate data bytes corresponding to the second disk block to generate intermediate results and generating a RAID syndrome based on, at least in part, the intermediate results. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于生成RAID综合征的方法。在一个实施例中，该方法可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节从存储设备加载到算术逻辑单元。该方法还可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节进行异或，以产生第一结果并将第一结果存储在结果缓冲器中。该方法还可以包括将对应于第一磁盘块的中间数据字节和对应于第二磁盘块的中间数据字节从存储设备反复重复加载到算术逻辑单元。该方法还可以包括对与第一磁盘块相对应的中间数据字节和对应于第二磁盘块的中间数据字节进行异或，以产生中间结果，并至少部分地基于中间结果生成RAID综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

39. 发明申请

US20050149744A1 Network processor having cryptographic processing including an authentication buffer 审中-公开
标题翻译：具有加密处理的网络处理器，包括认证缓冲器
公开(公告)号：US20050149744A1
公开(公告)日：2005-07-07
申请号：US10749913
申请日：2003-12-29
申请人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
发明人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
IPC分类号： G06F21/00 , H04L9/32 , H04L29/06
CPC分类号： H04L63/0428 , G06F21/72 , H04L9/32 , H04L63/08
摘要： A network processing having cryptographic processing includes an authentication buffer for storing ciphered data and providing the ciphered data to an authentication core.
摘要翻译：具有加密处理的网络处理包括用于存储加密数据并将加密数据提供给认证核心的认证缓冲器。

40. 发明申请

US20050141715A1 Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor 失效
标题翻译：用于在可编程网络处理器中调度由密码算法核心执行的命令的处理的方法和装置
公开(公告)号：US20050141715A1
公开(公告)日：2005-06-30
申请号：US10747852
申请日：2003-12-29
申请人： Jaroslaw Sydir , Chen-Chi Kuo , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
发明人： Jaroslaw Sydir , Chen-Chi Kuo , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
IPC分类号： H04K1/00
CPC分类号： G06F9/505 , G06F9/5033
摘要： A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.
摘要翻译：一种用于通过网络处理器中的多个加密算法核心调度命令处理的方法和装置。

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