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31. 发明授权

US07265013B2 Sidewall image transfer (SIT) technologies 失效
标题翻译：侧墙图像传输（SIT）技术
公开(公告)号：US07265013B2
公开(公告)日：2007-09-04
申请号：US11162662
申请日：2005-09-19
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Kirk D. Peterson
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Kirk D. Peterson
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28132
摘要： A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces of the structure. Then, portions of the conformal protective layer are removed so as to expose the capping region to the surrounding ambient without exposing the memory region to the surrounding ambient. Then, the capping region is removed so as to expose the positioning region to the surrounding ambient. Then, the positioning region is removed so as to expose the memory region to the surrounding ambient. Then, the memory region is directionally etched with remaining portions of the conformal protection layer serving as a blocking mask.
摘要翻译：一种结构制造方法。该方法包括提供一种结构，该结构包括：（a）待蚀刻层，（b）存储区域，（c）位于彼此顶部的定位区域（d）和封盖区域。然后，定位区域缩进。然后，在结构的暴露于环境的表面上形成保形层。然后，去除保形层的一部分，以将覆盖区域暴露于周围环境，而不会使存储区域暴露于周围环境。然后，去除封盖区域，以将定位区域暴露于周围环境。然后，移除定位区域，以将存储区域暴露于周围环境。然后，存储区域被定向蚀刻，保形层的剩余部分用作阻挡掩模。

32. 发明授权

US08629008B2 Electrical isolation structures for ultra-thin semiconductor-on-insulator devices 有权
标题翻译：用于超薄绝缘体上半导体器件的电气隔离结构
公开(公告)号：US08629008B2
公开(公告)日：2014-01-14
申请号：US13348018
申请日：2012-01-11
申请人： Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L21/02
CPC分类号： H01L29/0653 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.
摘要翻译：在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。沉积至少一个接触电介质层。可以在接触通孔内形成与手柄基板电隔离的结构的接触。

33. 发明授权

US08541823B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08541823B2
公开(公告)日：2013-09-24
申请号：US13179635
申请日：2011-07-11
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
摘要翻译：晶体管。晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

34. 发明申请

US20130175622A1 ELECTRICAL ISOLATION STRUCTURES FOR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
标题翻译：用于超薄半导体绝缘体器件的电气隔离结构
公开(公告)号：US20130175622A1
公开(公告)日：2013-07-11
申请号：US13348018
申请日：2012-01-11
申请人： Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.
摘要翻译：在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。沉积至少一个接触电介质层。可以在接触通孔内形成与手柄基板电隔离的结构的接触。

35. 发明授权

US08349674B2 Forming borderless contact for transistors in a replacement metal gate process 有权
标题翻译：在替代金属栅极工艺中形成晶体管的无边界接触
公开(公告)号：US08349674B2
公开(公告)日：2013-01-08
申请号：US13073151
申请日：2011-03-28
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/41733 , H01L29/41783 , H01L29/4966 , H01L29/6653 , H01L29/66553
摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.
摘要翻译：本发明的实施例提供了形成半导体结构的方法。该方法包括在电介质层内形成开口，介电层形成在衬底的顶部，并且该开口暴露衬底中晶体管的沟道区; 沉积衬套开口并覆盖通道区域的功函数层; 形成覆盖所述功函数层的第一部分的栅极导体，所述功函数层的所述第一部分位于所述沟道区的顶部; 并且去除所述功函数层的第二部分，所述功函数层的包围所述功函数层的第一部分的所述第二部分，其中所述功函数层的所述第二部分的去除使所述功函数层的第一部分绝缘工作功能层的工作功能层。

36. 发明申请

US20120329275A1 BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS 有权
公开(公告)号：US20120329275A1
公开(公告)日：2012-12-27
申请号：US13607677
申请日：2012-09-08
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L21/76885 , H01L21/76897 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

37. 发明申请

US20120248508A1 FORMING BORDERLESS CONTACT FOR TRANSISTORS IN A REPLACEMENT METAL GATE PROCESS 有权
标题翻译：在替代金属门过程中形成晶体管的无边界接触
公开(公告)号：US20120248508A1
公开(公告)日：2012-10-04
申请号：US13073151
申请日：2011-03-28
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/41733 , H01L29/41783 , H01L29/4966 , H01L29/6653 , H01L29/66553
摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.
摘要翻译：本发明的实施例提供一种形成半导体结构的方法。该方法包括在电介质层内形成开口，介电层形成在衬底的顶部，并且该开口暴露衬底中晶体管的沟道区; 沉积衬套开口并覆盖通道区域的功函数层; 形成覆盖所述功函数层的第一部分的栅极导体，所述功函数层的所述第一部分位于所述沟道区的顶部; 并且去除所述功函数层的第二部分，所述功函数层的包围所述功函数层的第一部分的所述第二部分，其中所述功函数层的所述第二部分的去除使所述功函数层的第一部分绝缘工作功能层的工作功能层。

38. 发明申请

US20120187566A1 AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION 有权
标题翻译：空气介质用于分层蚀刻线和通过金属化
公开(公告)号：US20120187566A1
公开(公告)日：2012-07-26
申请号：US13013108
申请日：2011-01-25
申请人： David V. Horak , Elbert Huang , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Elbert Huang , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/522 , H01L21/76802 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.
摘要翻译：公开了一种方法和结构，其中可以形成具有位于最容易受电容耦合的区域中的有效气隙的多个互连层。该方法包括提供导电特征层，所述层包括设置在基底上并彼此隔开小于或等于有效距离的至少两个线构件，以及至少一个这样的线构件，其还具有延伸的通孔构件离开基板，沉积不良共形介电涂层以在这些线构件之间形成气隙，并露出通孔的顶端。

39. 发明申请

US20120086128A1 BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS 有权
标题翻译：无边界连接线结构自上而下
公开(公告)号：US20120086128A1
公开(公告)日：2012-04-12
申请号：US12899911
申请日：2010-10-07
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/528 , H01L21/76885 , H01L21/76897 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
摘要翻译：金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准。沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。

40. 发明授权

US08138100B2 Microelectronic structure by selective deposition 有权
标题翻译：微电子结构通过选择性沉积
公开(公告)号：US08138100B2
公开(公告)日：2012-03-20
申请号：US12273908
申请日：2008-11-19
申请人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795 , H01L29/78645
摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.
摘要翻译： finFET结构包括位于衬底上的半导体鳍片。栅电极穿过半导体鳍片。栅电极具有邻接其侧壁的间隔层。间隔层不完全覆盖半导体鳍片的侧壁。栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上，而不是在衬底的邻接表面上，使得间隔层不完全覆盖半导体的侧壁鳍。可以使用侧向生长方法制造其它微电子结构。

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