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31. 发明授权

US08525162B2 Method of isolating nanowires from a substrate 有权
标题翻译：从衬底分离纳米线的方法
公开(公告)号：US08525162B2
公开(公告)日：2013-09-03
申请号：US13291682
申请日：2011-11-08
申请人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
发明人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
IPC分类号： H01L29/08
CPC分类号： H01L29/06 , B82Y99/00 , H01L21/76205 , H01L21/76224 , H01L29/0657 , H01L29/66795 , H01L29/775 , H01L29/7854
摘要： A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
摘要翻译：提供了一种方法。该方法包括在衬底的顶表面上形成多个纳米线并形成与多个纳米线中的每一个的底表面相邻的氧化物层，其中氧化物层将多个纳米线与衬底隔离。

32. 发明申请

US20100163838A1 METHOD OF ISOLATING NANOWIRES FROM A SUBSTRATE 有权
标题翻译：从基材中分离纳米微粒的方法
公开(公告)号：US20100163838A1
公开(公告)日：2010-07-01
申请号：US12346554
申请日：2008-12-30
申请人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
发明人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
IPC分类号： H01L29/06 , H01L21/20 , H01L21/762
CPC分类号： H01L29/06 , B82Y99/00 , H01L21/76205 , H01L21/76224 , H01L29/0657 , H01L29/66795 , H01L29/775 , H01L29/7854
摘要： A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
摘要翻译：提供了一种方法。该方法包括在衬底的顶表面上形成多个纳米线并形成与多个纳米线中的每一个的底表面相邻的氧化物层，其中氧化物层将多个纳米线与衬底隔离。

33. 发明授权

US08883573B2 Isolation for nanowire devices 有权
标题翻译：纳米线器件隔离
公开(公告)号：US08883573B2
公开(公告)日：2014-11-11
申请号：US13563456
申请日：2012-07-31
申请人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
发明人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
IPC分类号： H01L21/335 , H01L29/06 , H01L29/78 , H01L21/02 , B82Y10/00 , B82Y40/00 , H01L21/762 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0669 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L2221/1094
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
摘要翻译：本公开涉及制造微电子器件的领域。在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构提供用于在其上形成微电子结构的基本水平的表面。

34. 发明申请

US20130062594A1 METHOD OF ISOLATING NANOWIRES FROM A SUBSTRATE 有权
公开(公告)号：US20130062594A1
公开(公告)日：2013-03-14
申请号：US13291682
申请日：2011-11-08
申请人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
发明人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
IPC分类号： H01L29/06 , H01L29/775
CPC分类号： H01L29/06 , B82Y99/00 , H01L21/76205 , H01L21/76224 , H01L29/0657 , H01L29/66795 , H01L29/775 , H01L29/7854
摘要： A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

35. 发明授权

US08987091B2 III-N material structure for gate-recessed transistors 有权
标题翻译：用于栅极 - 凹槽晶体管的III-N材料结构
公开(公告)号：US08987091B2
公开(公告)日：2015-03-24
申请号：US13976840
申请日：2011-12-23
申请人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
发明人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336 , H01L31/00 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/778 , H01L29/40 , H01L29/20
CPC分类号： H01L29/7787 , H01L21/02241 , H01L21/02252 , H01L21/02255 , H01L21/02258 , H01L21/02458 , H01L21/0254 , H01L21/268 , H01L21/30604 , H01L21/30612 , H01L21/31111 , H01L29/2003 , H01L29/205 , H01L29/365 , H01L29/401 , H01L29/4236 , H01L29/512 , H01L29/518 , H01L29/66462
摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
摘要翻译：具有凹入栅极的III-N晶体管。外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和III-N沟道层之间的III-N蚀刻停止层。蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化物的凹陷栅III-N MOS-HEMT。可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。

36. 发明申请

US20140103397A1 TECHNIQUES FOR FORMING NON-PLANAR GERMANIUM QUANTUM WELL DEVICES 审中-公开
标题翻译：用于形成非平板锗量子阱器件的技术
公开(公告)号：US20140103397A1
公开(公告)日：2014-04-17
申请号：US14141648
申请日：2013-12-27
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译：公开了用于形成非平面锗量子阱结构的技术。特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。栅极金属可以跨鳍片结构沉积。排水/源极区域可以形成在翅片结构的相应端部处。

37. 发明申请

US20110147711A1 NON-PLANAR GERMANIUM QUANTUM WELL DEVICES 有权
标题翻译：非平面德国量子井设备
公开(公告)号：US20110147711A1
公开(公告)日：2011-06-23
申请号：US12646477
申请日：2009-12-23
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号： H01L29/06 , H01L21/338
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译：公开了用于形成非平面锗量子阱结构的技术。特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。栅极金属可以跨鳍片结构沉积。排水/源极区域可以形成在翅片结构的相应端部处。

38. 发明申请

US20090206404A1 REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY SILICIDATION 审中-公开
标题翻译：通过硅胶减少多门装置的外部电阻
公开(公告)号：US20090206404A1
公开(公告)日：2009-08-20
申请号：US12032588
申请日：2008-02-15
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Titash Rakshit , Robert S. Chau , Uday Shah
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Titash Rakshit , Robert S. Chau , Uday Shah
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7853 , H01L2029/7858
摘要： Reducing external resistance of a multi-gate device by silicidation is generally described. In one example, an apparatus includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a first surface, a second surface, and a third surface, the multi-gate fin also having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions wherein the source and drain regions of the multi-gate fin are fully or substantially silicized with a metal silicide, and a spacer dielectric material coupled to the first surface and the second surface wherein the spacer dielectric material substantially covers the first surface and the second surface in the source and drain regions.
摘要翻译：通常描述通过硅化物来减少多栅极器件的外部电阻。在一个示例中，设备包括半导体衬底，与半导体衬底耦合的多栅极鳍，多栅极翅片具有第一表面，第二表面和第三表面，多栅极鳍片还具有栅极所述栅极区域设置在所述源极和漏极区域之间，其中所述多栅极鳍片的源极和漏极区域用金属硅化物完全或基本上硅化，并且间隔物电介质材料耦合到第一表面和第二表面，其中间隔绝缘材料基本上覆盖源极和漏极区域中的第一表面和第二表面。

39. 发明授权

US08283653B2 Non-planar germanium quantum well devices 有权
标题翻译：非平面锗量子阱器件
公开(公告)号：US08283653B2
公开(公告)日：2012-10-09
申请号：US12646477
申请日：2009-12-23
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译：公开了用于形成非平面锗量子阱结构的技术。特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。栅极金属可以跨鳍片结构沉积。排水/源极区域可以形成在翅片结构的相应端部处。

40. 发明授权

US08264048B2 Multi-gate device having a T-shaped gate structure 有权
标题翻译：具有T形门结构的多门装置
公开(公告)号：US08264048B2
公开(公告)日：2012-09-11
申请号：US12032603
申请日：2008-02-15
申请人： Willy Rachmady , Uday Shah , Jack T. Kavalieros
发明人： Willy Rachmady , Uday Shah , Jack T. Kavalieros
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42376 , H01L21/28114 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A multi-gate device having a T-shaped gate structure is generally described. In one example, an apparatus includes a semiconductor substrate, at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a gate region, a source region, and a drain region, the gate region being positioned between the source and drain regions, a gate dielectric coupled to the gate region of the multi-gate fin, a gate electrode coupled to the gate dielectric, the gate electrode having a first thickness and a second thickness, the second thickness being greater than the first thickness, a first spacer dielectric coupled to a portion of the gate electrode having the first thickness, and a second spacer dielectric coupled to the first spacer dielectric and coupled to the gate electrode where the second spacer dielectric is coupled to a portion of the gate electrode having the second thickness.
摘要翻译：通常描述具有T形栅极结构的多栅极器件。在一个示例中，设备包括半导体衬底，与半导体衬底耦合的至少一个多栅极鳍，多栅极鳍具有栅极区，源极区和漏极区，栅极区位于源极和漏极区域，耦合到多栅极鳍的栅极区域的栅极电介质，耦合到栅极电介质的栅电极，栅电极具有第一厚度和第二厚度，第二厚度大于第一厚度耦合到具有第一厚度的栅电极的一部分的第一间隔电介质和耦合到第一间隔电介质并耦合到栅电极的第二间隔电介质，其中第二间隔电介质耦合到栅电极的一部分，第二厚度。

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