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31. 发明申请

US20160336417A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160336417A1
公开(公告)日：2016-11-17
申请号：US14749610
申请日：2015-06-24
申请人： UNITED MICROELECTRONICS CORP.
发明人： Shih-Yin Hsiao , Kun-Huang Yu , Nien-Chung Li , Wen-Fang Lee , Chih-Chung Wang
IPC分类号： H01L29/423 , H01L27/088 , H01L29/51 , H01L29/66 , H01L21/8234 , H01L29/06
CPC分类号： H01L29/42368 , H01L21/28167 , H01L21/3085 , H01L21/823462 , H01L21/823481 , H01L27/088 , H01L29/0653 , H01L29/66545 , H01L29/66613 , H01L29/66621 , H01L29/78
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; using a first patterned mask to form a gate dielectric layer on the substrate; removing the first patterned mask; removing part of the gate dielectric layer; and forming a shallow trench isolation (STI) adjacent to two sides of the gate dielectric layer.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供衬底; 使用第一图案化掩模在衬底上形成栅极电介质层; 去除第一图案化掩模; 去除所述栅介电层的一部分; 以及在所述栅极介电层的两侧形成浅沟槽隔离（STI）。

32. 发明授权

US09224859B1 High voltage metal-oxide-semiconductor transistor device 有权
标题翻译：高压金属氧化物半导体晶体管器件
公开(公告)号：US09224859B1
公开(公告)日：2015-12-29
申请号：US14590957
申请日：2015-01-06
申请人： UNITED MICROELECTRONICS CORP.
发明人： Shih-Chieh Pu , Ming-Tsung Lee , Cheng-Hua Yang , Nien-Chung Li , Wen-Fang Lee , Chih-Chung Wang
IPC分类号： H01L29/78 , H01L29/417 , H01L29/772 , H01L29/10 , H01L29/08
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/063 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/1045 , H01L29/7835
摘要： A high voltage metal-oxide-semiconductor (HV MOS) device includes a substrate including a first conductivity type, a gate positioned on the substrate, a drain region formed in the substrate, the drain region including a second conductivity type, and a source region formed in the substrate, where the source region includes at least one first part and at least one second part, the first part includes the second conductivity type, the second part includes the first conductivity type, and the first conductivity type and the second conductivity type are complementary.
摘要翻译：一种高电压金属氧化物半导体（HV MOS）器件包括：包括第一导电类型的衬底，位于衬底上的栅极，形成在衬底中的漏极区，包括第二导电类型的漏极区和源极区形成在基板中，其中源区域包括至少一个第一部分和至少一个第二部分，第一部分包括第二导电类型，第二部分包括第一导电类型，第一导电类型和第二导电类型是互补的

33. 发明授权

US09196717B2 High voltage metal-oxide-semiconductor transistor device 有权
标题翻译：高压金属氧化物半导体晶体管器件
公开(公告)号：US09196717B2
公开(公告)日：2015-11-24
申请号：US13629609
申请日：2012-09-28
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ming-Shun Hsu , Ke-Feng Lin , Chih-Chung Wang
IPC分类号： H01L29/78 , H01L29/06 , H01L29/08
CPC分类号： H01L29/78 , H01L29/063 , H01L29/0653 , H01L29/0692 , H01L29/0878 , H01L29/7816
摘要： A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.
摘要翻译：提供HV MOS晶体管器件。 HV MOS晶体管器件包括至少包括形成在其上的绝缘区域的衬底，位于衬底上并覆盖绝缘区域的一部分的栅极，形成在衬底中的栅极的各个侧面处的漏极区域和源极区域，以及形成在所述绝缘区域下方的第一注入区域。衬底包括第一导电类型，漏极，源极和第一注入区域包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

34. 发明申请

US20140339636A1 HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE 有权
标题翻译：高电压金属氧化物半导体晶体管器件
公开(公告)号：US20140339636A1
公开(公告)日：2014-11-20
申请号：US13896289
申请日：2013-05-16
申请人： United Microelectronics Corp.
发明人： Ming-Shun Hsu , Ke-Feng Lin , Chiu-Te Lee , Chih-Chung Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/823807 , H01L21/823814 , H01L27/085 , H01L27/088 , H01L27/0922 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0878
摘要： A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.
摘要翻译：高压金属氧化物半导体（HV MOS）晶体管器件包括衬底，形成在衬底中的漂移区域，形成在漂移区域中并由漂移区域彼此分开的多个隔离结构，多个分别形成在隔离结构中的掺杂岛，形成在衬底上的栅极，以及在栅极的相应两侧形成在衬底中的源极区和漏极区。门覆盖每个隔离结构的一部分。漂移区域，源区域和漏极区域包括第一导电类型，掺杂岛包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

35. 发明申请

US20140225192A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20140225192A1
公开(公告)日：2014-08-14
申请号：US14253365
申请日：2014-04-15
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chiu-Te Lee , Ke-Feng Lin , Shu-Wen Lin , Kun-Huang Yu , Chih-Chung Wang , Te-Yuan Wu
IPC分类号： H01L29/78 , H01L29/10 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/0878 , H01L29/407
摘要： A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.
摘要翻译：半导体结构包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。导电插头的第二部分的底表面被隔离层覆盖。

36. 发明申请

US20140131797A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20140131797A1
公开(公告)日：2014-05-15
申请号：US13674146
申请日：2012-11-12
申请人： UNITED MICROELECTRONICS CORP.
发明人： Wei-Lin Chen , Chih-Chien Chang , Ke-Feng Lin , Chiu-Te Lee , Chih-Chung Wang , Chiu-Ling Lee
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/0878 , H01L29/41766 , H01L29/66681
摘要： A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.
摘要翻译：半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且从衬底的表面向下延伸，并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插塞穿透隔离并到达其底部; 以及具有第二导电类型的第一掺杂电极区域，形成在第二阱内并在隔离件下方以连接导电插塞。

37. 发明申请

US20140091389A1 HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE 有权
标题翻译：高电压金属氧化物半导体晶体管器件
公开(公告)号：US20140091389A1
公开(公告)日：2014-04-03
申请号：US13629608
申请日：2012-09-28
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ming-Shun Hsu , Ke-Feng Lin , Chiu-Te Lee , Chih-Chung Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L29/063 , H01L29/0653 , H01L29/0692 , H01L29/7816
摘要： A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.
摘要翻译：高电压金属氧化物半导体晶体管器件包括其中形成有绝缘区域的衬底，覆盖绝缘区域的一部分并形成在衬底上的栅极，形成在栅极各侧的源极区域和漏极区域基板，形成在基板中并与栅极部分重叠的主体区域，以及形成在栅极下方并与主体区域相邻的基板中的第一注入区域。衬底和体区包括第一导电类型。源极区域，漏极区域和第一注入区域包括第二导电类型。第一导电类型和第二导电类型彼此互补。

38. 发明授权

US10497805B2 Semiconductor structure and manufacturing method of the same 有权
公开(公告)号：US10497805B2
公开(公告)日：2019-12-03
申请号：US16102847
申请日：2018-08-14
申请人： UNITED MICROELECTRONICS CORP.
发明人： Shin-Hung Li , Kuan-Chuan Chen , Nien-Chung Li , Wen-Fang Lee , Chih-Chung Wang
IPC分类号： H01L21/324 , H01L29/78 , H01L29/423 , H01L29/08 , H01L29/36 , H01L29/06 , H01L27/02 , G03F1/36 , H01L21/308 , H01L21/265 , H01L21/762 , H01L27/088 , H01L29/66
CPC分类号： H01L29/7833 , G03F1/36 , H01L21/26513 , H01L21/3086 , H01L21/324 , H01L21/76224 , H01L27/0207 , H01L27/088 , H01L29/0649 , H01L29/0847 , H01L29/36 , H01L29/42372 , H01L29/66575
摘要： A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.

39. 发明授权

US10453938B2 Transistor with dual spacer and forming method thereof 有权
公开(公告)号：US10453938B2
公开(公告)日：2019-10-22
申请号：US15846150
申请日：2017-12-18
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chia-Ling Wang , Ping-Hung Chiang , Chang-Po Hsiung , Chia-Wen Lu , Nien-Chung Li , Wen-Fang Lee , Chih-Chung Wang
IPC分类号： H01L29/66 , H01L27/088 , H01L29/08 , H01L29/78 , H01L21/311 , H01L21/8234 , H01L29/423 , H01L29/06
摘要： A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

40. 发明授权

US10431655B2 Transistor structure 有权
公开(公告)号：US10431655B2
公开(公告)日：2019-10-01
申请号：US15924001
申请日：2018-03-16
申请人： United Microelectronics Corp.
发明人： Yen-Ming Chen , Chiu-Ling Lee , Min-Hsuan Tsai , Chiu-Te Lee , Chih-Chung Wang
IPC分类号： H01L29/10 , H01L29/06 , H01L29/78 , H01L29/08
摘要： A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.

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