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    • 31. 发明授权
    • Bias circuit and semiconductor integrated circuit including the bias circuit
    • 偏置电路和半导体集成电路包括偏置电路
    • US07834701B2
    • 2010-11-16
    • US12519291
    • 2008-05-28
    • Tsuyoshi MatsushitaKoji OkaJunichi Naka
    • Tsuyoshi MatsushitaKoji OkaJunichi Naka
    • H03F3/04
    • H03F3/45475H03F1/0261H03F1/34H03F3/3022H03F3/347H03F3/45928H03F3/68H03F2203/45136
    • A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.
    • 多个模拟信号通过各自的电容器C输入到模拟信号处理电路ANA2的输入端子。在偏置电路Bias中,用于向模拟信号处理电路ANA2提供诸如模拟信号的信号地的偏置电压, 运算放大器OpAS,偏置电压VIr从内置差分放大器电路的非反相输入VIP输入,内置输出放大器电路OA1的输出端连接到差分放大器的反相输入端VIM 放大电路DA,从而获得电压跟随器。 此外,设置多个输出放大器电路OA2至OAn,使得其输入端连接到差分放大器电路DA的输出端,并且输出端连接到模拟信号处理电路ANA2的输入端IN1至INn。
    • 32. 发明申请
    • BIAS CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE BIAS CIRCUIT
    • 偏置电路和半导体集成电路,包括偏置电路
    • US20100045382A1
    • 2010-02-25
    • US12519291
    • 2008-05-28
    • Tsuyoshi MatsushitaKoji OkaJunichi Naka
    • Tsuyoshi MatsushitaKoji OkaJunichi Naka
    • H03F3/34
    • H03F3/45475H03F1/0261H03F1/34H03F3/3022H03F3/347H03F3/45928H03F3/68H03F2203/45136
    • A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.
    • 多个模拟信号通过各自的电容器C输入到模拟信号处理电路ANA2的输入端子。在偏置电路Bias中,用于向模拟信号处理电路ANA2提供诸如模拟信号的信号地的偏置电压, 运算放大器OpAS,偏置电压VIr从内置差分放大器电路的非反相输入VIP输入,内置输出放大器电路OA1的输出端连接到差分放大器的反相输入端VIM 放大电路DA,从而获得电压跟随器。 此外,设置多个输出放大器电路OA2至OAn,使得其输入端连接到差分放大器电路DA的输出端,并且输出端连接到模拟信号处理电路ANA2的输入端IN1至INn。
    • 33. 发明授权
    • Cleaning apparatus using compressed air
    • 使用压缩空气的清洁设备
    • US07234195B2
    • 2007-06-26
    • US10471034
    • 2003-06-26
    • Tsuyoshi Matsushita
    • Tsuyoshi Matsushita
    • B08B9/027
    • B08B9/0325B08B9/0326B08B9/0328
    • A cleaning apparatus has a compressor (12), an electromagnetic valve (33) connected to the compressor (12), and first to third timers (27 to 29). The first timer (27) sets an open/close time and a close time for repeatedly opening and closing an electromagnetic valve (33). The second timer (28) sets a time for feeding compressed air into a pipe (35). The third timer (29) stops the operation of the second timer (28) until an activation inhibition time elapses from a point at which the pressure of the compressed air has reached a predetermined upper limit, and further permits the operation of the second timer (28) after the activation inhibition time elapses.
    • 清洁装置具有压缩机(12),与压缩机(12)连接的电磁阀(33)和第一至第三定时器(27〜29)。 第一定时器27设定用于重复打开和关闭电磁阀33的打开/关闭时间和关闭时间。 第二定时器(28)设定将压缩空气供给到管道(35)中的时间。 第三计时器(29)停止第二定时器(28)的操作,直到从压缩空气的压力达到预定上限的点起经过激活禁止时间为止,并且进一步允许第二定时器 28),经过激活抑制时间。
    • 35. 发明授权
    • Negative feed-back amplifier and method for negative feed-back
    • 负反馈放大器和负反馈方法
    • US06593813B2
    • 2003-07-15
    • US09872730
    • 2001-06-01
    • Tsuyoshi Matsushita
    • Tsuyoshi Matsushita
    • H03F326
    • H03F1/3217H03F1/307
    • A negative feed-back amplifier is provided in which a distortion of signals is reduced and a dynamic range is increased. An input signal is input to a base of a transistor and is output from a collector as a reversed signal and a non-reversed signal is output from an emitter. The reversed signal is input to a base of a transistor and is output through a resistor from an emitter of the transistor. The non-reversed signal is input through a condenser to a base of a transistor and is output from a collector in a reversed form. An output signal from the transistor is input to an emitter follower of a transistor at high input impedance and output at low output impedance and then attenuated by resistors and negative feed-back signal is produced. The negative feed-back signal is input through a resistor to a base of the transistor to be added to the input signal.
    • 提供了一种负反馈放大器,其中信号的失真减小并且动态范围增加。 输入信号被输入到晶体管的基极,并且作为反向信号从集电极输出,并且从发射极输出非反相信号。 反相信号被输入到晶体管的基极,并且通过来自晶体管的发射极的电阻器输出。 非反相信号通过电容器输入到晶体管的基极,并以反向形式从集电极输出。 来自晶体管的输出信号被输入到高输入阻抗的晶体管的射极跟随器,并以低输出阻抗输出,然后由电阻衰减并产生负反馈信号。 负反馈信号通过电阻器输入到晶体管的基极以添加到输入信号。
    • 37. 发明授权
    • Memory device having backup power supply
    • 具有备用电源的存储器件
    • US4777626A
    • 1988-10-11
    • US807828
    • 1985-12-11
    • Tsuyoshi MatsushitaYoshiaki Ito
    • Tsuyoshi MatsushitaYoshiaki Ito
    • G06F1/24G11C5/14G11C7/22G11C7/24G11C7/00G11C11/40
    • G06F1/24G11C5/141G11C7/22G11C7/24
    • A memory device includes a reset signal generator for generating a reset signal when the output voltage from a main power supply circuit to supply a driving voltage to a memory decreases to a first predetermined voltage, and a switching circuit for allowing a data holding voltage from a backup power supply to be supplied to the memory in place of the driving voltage from the main power supply circuit in response to the reset signal. This memory device further includes a comparator for generating an inhibiting signal when it detects that the data holding voltage from the backup power supply following generation of the reset signal is lower than the voltage necessary to hold the data in the memory, and a control circuit for setting the memory into an operation inhibition state when it detects that the inhibiting signal was generated from the comparator following the reset signal.
    • 存储装置包括复位信号发生器,用于当来自主电源电路的输出电压向存储器提供驱动电压时产生复位信号,将其恢复到第一预定电压;以及切换电路,用于允许来自 替代来自主电源电路的驱动电压的备用电源被提供给存储器,以响应于复位信号。 该存储装置还包括一个比较器,用于在检测到复位信号产生之后的备用电源的数据保持电压低于将数据保持在存储器中所需的电压时,产生禁止信号;以及控制电路, 当检测到从复位信号后的比较器产生禁止信号时,将存储器设置为操作禁止状态。
    • 38. 发明授权
    • Dot character display apparatus
    • 点字显示装置
    • US4751508A
    • 1988-06-14
    • US820563
    • 1986-01-21
    • Tsuyoshi Matsushita
    • Tsuyoshi Matsushita
    • G09G3/20G09G5/24G09G1/00
    • G09G3/20G09G5/24
    • A dot character display apparatus includes a control circuit for transferring data corresponding to character body and upper and lower symbols from first to third character generators to image buffers, a drive circuit for driving a dot matrix display section on the basis of the data stored in the image buffers. The dot matrix display section has an upper display area to display the upper symbol, a central display area to display the charcter body, and a lower display area to display the lower symbol. The drive circuit has a first drive section to drive the central display area of the dot matrix display section in accordance with data indicative of the character body from the first character generator, and a secod drive section to drive the upper and lower display areas of the dot matrix display section in accordance with data representative of the upper and lower symbols from the second and third character generators.
    • 点字显示装置包括:控制电路,用于将与字体相对应的数据和从第一到第三字符发生器的上下符号传送到图像缓冲器;驱动电路,用于根据存储在 图像缓冲区 点阵显示部分具有显示上部符号的上部显示区域,用于显示特征体的中央显示区域和显示较低符号的下部显示区域。 驱动电路具有:第一驱动部,其根据来自第一字符发生器的字符体的数据,驱动点阵显示部的中央显示区域;驱动驱动部,驱动上述显示区域的上下显示区域; 点阵显示部分,根据表示来自第二和第三字符发生器的上部和下部符号的数据。