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31. 发明申请

US20050185355A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20050185355A1
公开(公告)日：2005-08-25
申请号：US11104541
申请日：2005-04-13
申请人： Kumiko Takikawa , Satoshi Tanaka , Masumi Kasahara
发明人： Kumiko Takikawa , Satoshi Tanaka , Masumi Kasahara
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H03F1/52 , H04B1/3822 , H04B1/40 , H02H1/00
CPC分类号： H01L27/0259 , H01L27/0255 , H03F1/52 , H03F2200/372
摘要： Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.
摘要翻译：在内部电路中工作在高频带内，结合有多级连接的保护电路，其被构造为包括具有低寄生电容并且没有故障的多个二极管连接的晶体管，即使当输入信号高于施加电源电压。在内部电路中工作在低频带，其中包括一个保护电路，其构造为包括一个二极管连接的晶体管。保护电路包括两条保护电路，其中电流方向相反，以保护内部电路免受正/负静电。

32. 发明授权

US08107912B2 Mobile communication apparatus 有权
标题翻译：移动通信装置
公开(公告)号：US08107912B2
公开(公告)日：2012-01-31
申请号：US12975488
申请日：2010-12-22
申请人： Satoshi Tanaka , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
发明人： Satoshi Tanaka , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
IPC分类号： H04B1/06 , H04B7/00 , H04B1/10
CPC分类号： H04B1/30 , H03D2200/0047 , H03K21/16
摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
摘要翻译：适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除消除。

33. 发明授权

US07800452B2 Phase locked loop circuit 失效
标题翻译：锁相环电路
公开(公告)号：US07800452B2
公开(公告)日：2010-09-21
申请号：US11976408
申请日：2007-10-24
申请人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
发明人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/107 , H03C3/0925 , H03C3/0941 , H03C3/0991 , H03L7/1974 , H03L7/1976
摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation.This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.
摘要翻译：本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

34. 发明申请

US20080182538A1 MOBILE COMMUNICATION APPARATUS 有权
标题翻译：手机通讯设备
公开(公告)号：US20080182538A1
公开(公告)日：2008-07-31
申请号：US12056576
申请日：2008-03-27
申请人： Satoshi TANAKA , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
发明人： Satoshi TANAKA , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
IPC分类号： H04B1/06 , H04B1/10
CPC分类号： H04B1/30 , H03D2200/0047 , H03K21/16
摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
摘要翻译：适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除消除。

35. 发明申请

US20080061890A1 Phase locked loop circuit 失效
标题翻译：锁相环电路
公开(公告)号：US20080061890A1
公开(公告)日：2008-03-13
申请号：US11976408
申请日：2007-10-24
申请人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
发明人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/107 , H03C3/0925 , H03C3/0941 , H03C3/0991 , H03L7/1974 , H03L7/1976
摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.
摘要翻译：本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

36. 发明申请

US20080030911A1 Semiconductor integrated circuit device 失效
公开(公告)号：US20080030911A1
公开(公告)日：2008-02-07
申请号：US11898946
申请日：2007-09-18
申请人： Kumiko Takikawa , Satoshi Tanaka , Masumi Kasahara
发明人： Kumiko Takikawa , Satoshi Tanaka , Masumi Kasahara
IPC分类号： H01C7/12
CPC分类号： H01L27/0259 , H01L27/0255 , H03F1/52 , H03F2200/372
摘要： Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.

37. 发明申请

US20060114074A1 Semiconductor integrated circuit for communication incorporating oscillator, communication system, and method for manufacturing the semiconductor integrated circuit 审中-公开
标题翻译：用于通信的半导体集成电路，包括振荡器，通信系统和用于制造半导体集成电路的方法
公开(公告)号：US20060114074A1
公开(公告)日：2006-06-01
申请号：US11289470
申请日：2005-11-30
申请人： Toshiki Matsui , Masumi Kasahara , Norio Hayashi
发明人： Toshiki Matsui , Masumi Kasahara , Norio Hayashi
IPC分类号： H03B5/12
CPC分类号： H03B5/366
摘要： A semiconductor integrated circuit for communication has a reference oscillator with high frequency control accuracy. The oscillator has a capacitive load circuit including a plurality of fixed capacitance elements, a plurality of variable capacitance elements, and switch elements connected to the capacitance elements, and is configured such that it can oscillate at a frequency corresponding to a synthesized capacitance value of the fixed capacitance elements, variable capacitance elements, and external oscillation elements. Through a control circuit that can generate a signal for controlling the switch elements, a combination of the variable capacitance element and the fixed capacitance element can be selected, in which the slopes of the characteristics of the frequency to control voltage are equalized, and intervals between the respective characteristic lines are equalized by the synthesized capacitance value of the capacitive load circuit and the oscillation elements.
摘要翻译：用于通信的半导体集成电路具有高频控制精度的基准振荡器。该振荡器具有包括多个固定电容元件，多个可变电容元件和连接到电容元件的开关元件的电容性负载电路，并且被配置为使得其可以以对应于电容元件的合成电容值的频率振荡固定电容元件，可变电容元件和外部振荡元件。通过可以产生用于控制开关元件的信号的控制电路，可以选择可变电容元件和固定电容元件的组合，其中使频率与控制电压的特性的斜率相等，并且可以选择各特性线由电容性负载电路和振荡元件的合成电容值相等。

38. 发明授权

US07504903B2 Communication semiconductor integrated circuit device and a wireless communication system 失效
标题翻译：通信半导体集成电路器件和无线通信系统
公开(公告)号：US07504903B2
公开(公告)日：2009-03-17
申请号：US11592982
申请日：2006-11-06
申请人： Masumi Kasahara , Hirotaka Osawa , Robert Astle Henshaw
发明人： Masumi Kasahara , Hirotaka Osawa , Robert Astle Henshaw
IPC分类号： H03B1/00
CPC分类号： H03L7/187 , H03L7/099
摘要： In a communication semiconductor integrated circuit device, an oscillator of a PLL circuit can operate in a plurality of frequency bands. With a control voltage (Vc) of the oscillator fixed to a predetermined value (VDC), an oscillation frequency of the oscillator is measured for each band to be stored in a storage. When the PLL operates, a setting value to specify a band is compared with the measured frequency values stored in the storage. As a result of the comparison, a band to be actually used by the oscillator is determined.
摘要翻译：在通信半导体集成电路器件中，PLL电路的振荡器可以在多个频带中工作。在振荡器的控制电压（Vc）固定为预定值（VDC）的情况下，对要存储在存储器中的每个频带测量振荡器的振荡频率。当PLL操作时，将指定频带的设定值与存储在存储器中的测量频率值进行比较。作为比较的结果，确定振荡器实际使用的频带。

39. 发明授权

US07278577B2 Image input system 有权
标题翻译：图像输入系统
公开(公告)号：US07278577B2
公开(公告)日：2007-10-09
申请号：US10823642
申请日：2004-04-14
申请人： Kouichi Yahagi , Masumi Kasahara , Hiroki Nakajima
发明人： Kouichi Yahagi , Masumi Kasahara , Hiroki Nakajima
IPC分类号： G06F7/10 , H03K3/00 , G06K7/10 , G06K15/12 , G06K7/14 , H03G3/32 , H04N5/20
CPC分类号： H04N5/378 , H04N5/3572 , H04N5/3575 , H04N5/361 , H04N5/3655
摘要： An image input system includes a solid state image pickup device and a preprocessor for performing correlated double sampling amplification on an output of the image pickup device and outputting a video signal. The preprocessor has a correlated double sampling amplifier for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the image pickup device and a signal level in a charge signal output period; and an offset cancelling circuit for cancelling an offset voltage corresponding to the difference voltage in a state where the image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other, so that circuits following the correlated double sampling amplifier are not influenced by the offset voltage.
摘要翻译：图像输入系统包括固态图像拾取装置和预处理器，用于对图像拾取装置的输出执行相关双重采样放大并输出视频信号。所述预处理器具有相关联的双采样放大器，用于输出对应于图像拾取装置的馈通周期中的黑电平与电荷信号输出周期中的信号电平之间的差电压的信号信息; 以及偏移消除电路，用于在图像拾取器件被光学地中断到相关双采样放大器的输入端的状态下消除对应于差分电压的偏移电压。相关双采样放大器消除偏移电压和偏移消除电压作为彼此相反极性的信号分量，使得相关双采样放大器之后的电路不受偏移电压的影响。

40. 发明申请

US20070007347A1 Image input system 审中-公开
标题翻译：图像输入系统
公开(公告)号：US20070007347A1
公开(公告)日：2007-01-11
申请号：US11434167
申请日：2006-05-16
申请人： Kouichi Yahagi , Masumi Kasahara , Hiroki Nakajima
发明人： Kouichi Yahagi , Masumi Kasahara , Hiroki Nakajima
IPC分类号： G06K7/10
CPC分类号： H04N5/378 , H04N5/3572 , H04N5/3575 , H04N5/361 , H04N5/3655
摘要： An image input system comprises a solid state image pickup device and a preprocessor (3) for performing correlated double sampling amplification on an output signal of the solid state image pickup device and outputting a video signal. The preprocessor comprises: a correlated double sampling amplifier (30) for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the solid state image pickup device and a signal level in a charge signal output period; and offset cancelling means (38) for applying an offset cancelling voltage for cancelling an offset voltage corresponding to the difference voltage between the black level and the signal level in a state where the solid state image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other. Circuits at the post stage of the correlated double sampling amplifier are not influenced by the offset voltage. Even if capacitive noise characteristics of the solid state image pickup device are not preferable, a high-grade image can be inputted.
摘要翻译：图像输入系统包括固态图像拾取装置和用于对固态图像拾取装置的输出信号执行相关双重采样放大并输出视频信号的预处理器（3）。预处理器包括：相关双采样放大器（30），用于输出与固态图像拾取装置的馈通周期中的黑电平和充电信号输出周期中的信号电平之间的差电压相对应的信号信息; 以及偏移消除装置（38），用于在固态图像拾取装置被光学地中断到所述黑电平和信号电平的输入端的状态下，施加用于抵消与黑电平和信号电平之间的差电压相对应的偏移电压的偏移消除电压相关双采样放大器。相关的双采样放大器消除偏移电压和偏移消除电压作为彼此相反极性的信号分量。相关双采样放大器后级的电路不受偏移电压的影响。即使固态摄像装置的电容噪声特性不优选，也可以输入高等级的图像。

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