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31. 发明授权

US07038967B2 Semiconductor apparatus capable of performing refresh control 有权
标题翻译：能够进行刷新控制的半导体装置
公开(公告)号：US07038967B2
公开(公告)日：2006-05-02
申请号：US10864814
申请日：2004-06-10
申请人： Toshitaka Uchikoba , Tomonori Fujimoto , Kiyoto Ohta
发明人： Toshitaka Uchikoba , Tomonori Fujimoto , Kiyoto Ohta
IPC分类号： G11C7/00 , G11C7/04
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40626
摘要： A semiconductor apparatus according to the present invention comprises a current source increasing a current volume in compliance with a rise of a temperature and an oscillation circuit driven by the current of the current source and outputting a clock for refresh control. The semiconductor apparatus, preferably, further comprises a memory device performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof. The semiconductor apparatus, preferably, further comprises a constant voltage source generating a constant voltage using the current source, an oscillation circuit using the current of the current source, and a memory using the constant voltage generated by the constant voltage source as a reference voltage for a power supply circuit and performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof.
摘要翻译：根据本发明的半导体装置包括电流源，其根据温度的升高增加电流体积，并且由电流源的电流驱动的振荡电路，并输出用于刷新控制的时钟。半导体装置优选地还包括与振荡电路的输出时钟或其分频时钟同步地执行刷新的存储器件。半导体装置优选地还包括使用电流源产生恒定电压的恒定电压源，使用电流源的电流的振荡电路和使用由恒定电压源产生的恒定电压作为参考电压的存储器电源电路，并且与振荡电路的输出时钟或其分频时钟同步地进行刷新。

32. 发明授权

US07002866B2 Semiconductor memory device 有权
公开(公告)号：US07002866B2
公开(公告)日：2006-02-21
申请号：US11078396
申请日：2005-03-14
申请人： Masanobu Hirose , Masahisa Iida , Kiyoto Ohta
发明人： Masanobu Hirose , Masahisa Iida , Kiyoto Ohta
IPC分类号： G11C7/02
CPC分类号： H01L27/10882 , G11C7/02 , G11C7/18 , H01L23/5225 , H01L27/10885 , H01L27/10897 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.

33. 发明授权

US06898109B2 Semiconductor memory device in which bit lines connected to dynamic memory cells extend left and right of sense amplifier column 有权
标题翻译：半导体存储器件，其中连接到动态存储单元的位线延伸到读出放大器列的左侧和右侧
公开(公告)号：US06898109B2
公开(公告)日：2005-05-24
申请号：US10299696
申请日：2002-11-20
申请人： Masanobu Hirose , Masahisa Iida , Kiyoto Ohta
发明人： Masanobu Hirose , Masahisa Iida , Kiyoto Ohta
IPC分类号： G11C11/401 , G11C7/18 , G11C11/409 , H01L21/3205 , H01L21/82 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/04 , H01L27/108 , G11C11/24
CPC分类号： H01L27/10882 , G11C7/02 , G11C7/18 , H01L23/5225 , H01L27/10885 , H01L27/10897 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.
摘要翻译：在单路交叉型（开路位线型）动态RAM中，子阵列设置在位于中心的读出放大器列的左侧和右侧。每个子阵列具有多个动态存储单元。在位于读出放大器列左侧和右侧的子阵列中，同一行中的位线构成互补的位线对。在每个子阵列中，与这些位线平行并且在同一布线层中形成的屏蔽布线图案设置在位线之间。所有这些布线图案被设置在固定电位，例如电源电位。因此，有效地减少相邻位线之间的干扰噪声。

34. 发明授权

US06785187B2 Semiconductor device having integrated memory and logic 失效
标题翻译：具有集成存储器和逻辑的半导体器件
公开(公告)号：US06785187B2
公开(公告)日：2004-08-31
申请号：US10325932
申请日：2002-12-23
申请人： Tomonori Fujimoto , Shoji Sakamoto , Kiyoto Ohta
发明人： Tomonori Fujimoto , Shoji Sakamoto , Kiyoto Ohta
IPC分类号： G11C800
CPC分类号： G11C11/4082 , G11C8/06 , G11C29/48
摘要： In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate. The present invention conducts this test through a scan test, making it possible to automatically create test patterns with high circuit failure detection rate.
摘要翻译：在常规DRAM中，行地址和列地址被DFF锁存，地址的解码在时钟上升之后的特定时间开始，并且在时钟上升直到解码完成之后需要很长时间，具有这样的问题不可能高速执行读/写。本发明采用使用扫描链连接诸如行地址锁存电路和列地址锁存电路的锁存电路的配置。这使得当时钟为“L”时，行地址和列地址的解码开始，使得可以在每个操作时钟周期的上升完成解码，缩短操作时钟周期并加快读/写速度。传统技术通过整个LSI的实际操作测试来对逻辑部分和存储器的行地址和列地址之间的连接进行测试，导致低电路故障检测率。本发明通过扫描测试进行该测试，使得可以自动创建具有高电路故障检测速率的测试图案。

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