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31. 发明授权

US06555429B2 Method of manufacturing semiconductor devices utilizing underlayer-dependency of deposition of capacitor electrode film, and semiconductor device 有权
公开(公告)号：US06555429B2
公开(公告)日：2003-04-29
申请号：US09810627
申请日：2001-03-19
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.

32. 发明授权

US06483143B2 Semiconductor device having a capacitor structure including a self-alignment deposition preventing film 有权
标题翻译：具有包括自对准防沉积膜的电容器结构的半导体器件
公开(公告)号：US06483143B2
公开(公告)日：2002-11-19
申请号：US09810401
申请日：2001-03-19
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L27108
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.
摘要翻译：在包括多个存储单元的半导体器件中，在形成有多个孔的层间绝缘膜上形成防沉积膜，或者在层间绝缘膜和内表面上选择性地形成晶种膜，孔的底面。在发生底层依赖性的条件下，通过化学气相沉积在沉积防止膜上或通过利用种子膜在层间绝缘膜上沉积Ru，Ir或Pt的膜。因此，根据防沉积膜或种子膜的图案形成下部电极。在预定温度下在下电极和防沉积膜上形成电介质膜。即使暴露在用于形成电介质膜的预定温度下，下电极的材料也不会导通。上电极进一步形成在电介质膜上。上下电极和氧化物介质膜一起构成存储单元的电容器。

33. 发明授权

US4848983A Catalytic coal gasification by utilizing chlorides 失效
标题翻译：催化煤气化利用氯化物
公开(公告)号：US4848983A
公开(公告)日：1989-07-18
申请号：US105351
申请日：1987-10-06
申请人： Akira Tomita , Yasuo Ohtsuka , Takayuki Takarada , Toshihide Nabatame
发明人： Akira Tomita , Yasuo Ohtsuka , Takayuki Takarada , Toshihide Nabatame
IPC分类号： C10J3/72 , C10J3/00
CPC分类号： C10J3/00 , C10J2300/093 , C10J2300/0973 , C10J2300/0986 , C10J2300/1853 , Y02P20/52
摘要： A process of catalytic coal gasification characterized by mixing an inexpensive, low rank coal with an aqueous solution of inexpensive, widely existing alkali metal or alkaline earth metal chlorides, such as Nacl, KCl, or the like; adding a pH adjustor such as ammonia to the resulting mixture to adjust pH to 5.about.12, whereby an ion exchange is effected between said metal and hydrogen in the coal, thereby loading only metals as a catalyst on the coal; washing the coal with water to remove chloride by-products; and running steam onto the catalyst-loaded coal at high temperatures and high pressures.
摘要翻译：一种催化煤气化方法，其特征在于将便宜的低等级煤与廉价广泛存在的碱金属或碱土金属氯化物如Nacl，KCl等的水溶液混合; 向所得混合物中加入pH调节剂如氨，将pH调节至5℃，由此在煤中的所述金属与氢之间进行离子交换，从而仅将作为催化剂的金属装载在煤上; 用水清洗煤以除去副产物; 并在高温和高压下将蒸汽运送到负载催化剂的煤上。

34. 发明授权

US08207584B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08207584B2
公开(公告)日：2012-06-26
申请号：US12329580
申请日：2008-12-06
申请人： Toshihide Nabatame , Kunihiko Iwamoto , Yuuichi Kamimuta
发明人： Toshihide Nabatame , Kunihiko Iwamoto , Yuuichi Kamimuta
IPC分类号： H01L21/02
CPC分类号： H01L21/823857
摘要： After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H2, thereby forming a dipole between the oxygen deficiency adjustment layer and the silicon oxide film. Then, the conductive film, the high dielectric constant film, the oxygen deficiency adjustment layer, the silicon oxide film and the like are patterned, thereby forming a gate electrode and a gate insulating film.
摘要翻译：在n型阱和p型阱的各个表面上形成纯氧化硅膜之后，由2A族元素的氧化物，3A族元素的氧化物，3B族元素的氧化物构成的氧缺乏调整层，4A族元素的氧化物，5A族元素的氧化物等，高介电常数膜和具有还原催化剂对氢的催化剂作用的导电膜依次沉积在氧化硅膜上，将基材热处理在含有H 2的气氛中，从而在缺氧调节层和氧化硅膜之间形成偶极子。然后，对导电膜，高介电常数膜，氧缺陷调节层，氧化硅膜等进行构图，从而形成栅电极和栅极绝缘膜。

35. 发明授权

US07820503B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07820503B2
公开(公告)日：2010-10-26
申请号：US12219897
申请日：2008-07-30
申请人： Toshihide Nabatame , Masaru Kadoshima , Hiroyuki Takaba
发明人： Toshihide Nabatame , Masaru Kadoshima , Hiroyuki Takaba
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28185 , H01L29/6659 , H01L29/7833
摘要： An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.
摘要翻译：本发明的一个目的是简化n沟道MIS晶体管和具有由金属材料形成的栅电极的p沟道MIS晶体管的制造工艺。为了实现，通过图案化沉积在栅极绝缘体上的钌膜，同时形成n沟道MIS晶体管和p沟道MIS晶体管中的每一个的栅电极。接下来，通过将氧气引入每个栅电极，将栅电极转变为具有高功函数的栅电极。此后，通过选择性地还原n沟道MIS晶体管的栅电极，将其转换成具有低功函数的栅电极。

36. 发明申请

US20080166867A1 Semiconductor device, method of manufacturing the same, and method of manufacturing metal compound thin film 有权
标题翻译：半导体装置及其制造方法以及金属化合物薄膜的制造方法
公开(公告)号：US20080166867A1
公开(公告)日：2008-07-10
申请号：US12001381
申请日：2007-12-11
申请人： Kunihiko Iwamoto , Toshihide Nabatame , Koji Tominaga , Tetsuji Yasuda
发明人： Kunihiko Iwamoto , Toshihide Nabatame , Koji Tominaga , Tetsuji Yasuda
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.
摘要翻译：公开了一种制造金属化合物薄膜的方法。该方法可以包括通过原子层沉积在衬底上形成第一金属化合物层，在含有氮化合物气体的气氛中对第一金属化合物层进行退火，从而将氮扩散到第一金属化合物层中，并形成第二金属通过原子层沉积在第一金属化合物层上的化合物层。

37. 发明授权

US07372112B2 Semiconductor device, process for producing the same and process for producing metal compound thin film 有权
标题翻译：半导体装置及其制造方法以及金属化合物薄膜的制造方法
公开(公告)号：US07372112B2
公开(公告)日：2008-05-13
申请号：US10550643
申请日：2005-03-24
申请人： Kunihiko Iwamoto , Toshihide Nabatame , Koji Tominaga , Tetsuji Yasuda
发明人： Kunihiko Iwamoto , Toshihide Nabatame , Koji Tominaga , Tetsuji Yasuda
IPC分类号： H01L29/792
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A high dielectric gate insulating film having the structure that a high-nitrogen layer, a low-nitrogen layer, and a high-nitrogen layer are layered in this order from a silicon-substrate side.
摘要翻译：具有高氮层，低氮层和高氮层的结构的高介电栅极绝缘膜从硅衬底侧依次层叠。

38. 发明授权

US07323381B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07323381B2
公开(公告)日：2008-01-29
申请号：US11180657
申请日：2005-07-14
申请人： Masaru Kadoshima , Toshihide Nabatame
发明人： Masaru Kadoshima , Toshihide Nabatame
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO2) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.
摘要翻译：提供了用于实现能够同时实现高导通电流和低功耗的CMOS电路的MIS晶体管的结构。 n沟道MIS晶体管和p沟道MIS晶体管的每个栅绝缘体由氧化铪（HfO 2 O 2）膜组成。此外，n沟道MIS晶体管的栅电极由Ni（镍）硅化物膜构成，p沟道MIS晶体管的栅电极由Pt（铂）膜构成。在这种结构中，可以防止栅电极的费米能级钉扎。因此，可以抑制n沟道MIS晶体管和p沟道MIS晶体管的阈值电压的增加。

39. 发明申请

US20070096157A1 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20070096157A1
公开(公告)日：2007-05-03
申请号：US11515797
申请日：2006-09-06
申请人： Toshihide Nabatame , Masaru Kadoshima , Hiroyuki Takaba
发明人： Toshihide Nabatame , Masaru Kadoshima , Hiroyuki Takaba
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L21/823842 , H01L21/28185 , H01L29/6659 , H01L29/7833
摘要： An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.
摘要翻译：本发明的一个目的是简化n沟道MIS晶体管和具有由金属材料形成的栅电极的p沟道MIS晶体管的制造工艺。为了实现，通过图案化沉积在栅极绝缘体上的钌膜，同时形成n沟道MIS晶体管和p沟道MIS晶体管中的每一个的栅电极。接下来，通过将氧气引入每个栅电极，将栅电极转变为具有高功函数的栅电极。此后，通过选择性地还原n沟道MIS晶体管的栅电极，将其转换成具有低功函数的栅电极。

40. 发明申请

US20060051915A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060051915A1
公开(公告)日：2006-03-09
申请号：US11180657
申请日：2005-07-14
申请人： Masaru Kadoshima , Toshihide Nabatame
发明人： Masaru Kadoshima , Toshihide Nabatame
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823842
摘要： A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO2) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.
摘要翻译：提供了用于实现能够同时实现高导通电流和低功耗的CMOS电路的MIS晶体管的结构。 n沟道MIS晶体管和p沟道MIS晶体管的每个栅绝缘体由氧化铪（HfO 2 O 2）膜组成。此外，n沟道MIS晶体管的栅电极由Ni（镍）硅化物膜构成，p沟道MIS晶体管的栅电极由Pt（铂）膜构成。在这种结构中，可以防止栅电极的费米能级钉扎。因此，可以抑制n沟道MIS晶体管和p沟道MIS晶体管的阈值电压的增加。

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