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31. 发明申请

US20090125706A1 Software Pipelining on a Network on Chip 审中-公开
标题翻译：网络芯片上的软件流水线
公开(公告)号：US20090125706A1
公开(公告)日：2009-05-14
申请号：US11936873
申请日：2007-11-08
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Paul E. Schardt
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Paul E. Schardt
IPC分类号： G06F9/38
CPC分类号： G06F9/5038 , G06F9/30047 , G06F9/3851 , G06F9/3885 , G06F15/7825 , G06F15/8053 , G06F2209/5017
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，其中每个存储器通信控制器控制IP块和存储器之间的通信以及控制通过路由器进行IP间块通信的每个网络接口控制器，NOC还包括被分段成阶段的计算机软件应用，每个级包括计算机程序的可灵活配置的模块由阶段ID标识的指令，每个阶段在IP块上的执行线程上执行。

32. 发明申请

US20090049452A1 Spawned Message State Determination 有权
标题翻译：产生消息状态确定
公开(公告)号：US20090049452A1
公开(公告)日：2009-02-19
申请号：US11837841
申请日：2007-08-13
申请人： Jon K. Kriegel , Mark Gary Kupferschmidt , Paul Emery Schardt
发明人： Jon K. Kriegel , Mark Gary Kupferschmidt , Paul Emery Schardt
IPC分类号： G06F3/00
CPC分类号： G06F9/546 , G06T15/005 , G06T15/06
摘要： According to embodiments of the invention, methods and apparatus are provided for tracking the status or state of a message spawned or sent from one processing element to another processing element in a multiple core processing element network. According to embodiments of the invention, a message status tracker may be incorporated within a multiple core processing element network. As a message is spawned or sent from an originating processing element to a receiving processing element, a counter within the message status tracker may be incremented. If the receiving processing element spawns further messages in response to the received message, the counter may be further incremented. When a receiving processing element finishes a process in response to a received message, the receiving processing element may decrement the counter. When the counter is decremented to an original value (e.g., zero) the original message may be considered complete.
摘要翻译：根据本发明的实施例，提供了用于跟踪在多核处理元件网络中从一个处理元件产生或发送到另一个处理元件的消息的状态或状态的方法和装置。根据本发明的实施例，消息状态跟踪器可以并入多核处理元件网络内。当消息从始发处理元件产生或发送到接收处理元件时，可以增加消息状态跟踪器内的计数器。如果接收处理元件响应于接收到的消息产生进一步的消息，则计数器可以进一步递增。当接收处理单元响应于接收到的消息完成处理时，接收处理单元可以递减计数器。当计数器递减到原始值（例如，零）时，原始消息可以被认为是完整的。

33. 发明申请

US20080263339A1 Method and Apparatus for Context Switching and Synchronization 失效
标题翻译：用于上下文切换和同步的方法和装置
公开(公告)号：US20080263339A1
公开(公告)日：2008-10-23
申请号：US11736936
申请日：2007-04-18
申请人： Jon K. Kriegel , Eric Oliver Mejdrich
发明人： Jon K. Kriegel , Eric Oliver Mejdrich
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F9/461 , G06F9/463 , G06F9/5016 , G06F9/5027 , G06F12/0837 , G06F12/0842 , G06F12/1054 , G06F12/126 , G06F2209/481 , G06F2209/5018
摘要： A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread.
摘要翻译：一种用于第一线程和第二线程之间的上下文切换的方法，计算机可读介质和装置。该方法包括检测异常，其中响应于接收到针对第一线程和第二线程之一的信息的分组而产生异常，并且响应于检测到该异常，调用异常处理程序。异常处理程序被配置为执行一个或多个指令，以移除对处理器高速缓存的至少一部分的访问。处理器缓存的部分包含使用第一个地址转换的第一个线程的缓存信息。去除对处理器高速缓存部分的访问阻止使用第二地址转换的第二线程访问处理器高速缓存中的缓存信息。异常处理程序还被配置为分支到第一线程和第二线程中的至少一个。

34. 发明申请

US20080028403A1 Method and Apparatus for Communicating Between Threads 有权
标题翻译：用于在线程之间进行通信的方法和装置
公开(公告)号：US20080028403A1
公开(公告)日：2008-01-31
申请号：US11567882
申请日：2006-12-07
申请人： Russell Dean Hoover , Jon K. Kriegel , Eric Oliver Mejdrich , Robert Allen Shearer
发明人： Russell Dean Hoover , Jon K. Kriegel , Eric Oliver Mejdrich , Robert Allen Shearer
IPC分类号： G06F9/46
CPC分类号： G06T15/50 , G06T15/06
摘要： A method and apparatus for communicating between threads in a processor. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from a second thread, wherein the packet includes an access request. The method further includes using inbox control circuitry for the inbox to process the received packet and determine whether to grant the access request included in the packet.
摘要翻译：一种用于在处理器中的线程之间进行通信的方法和装置。该方法包括在收件箱的处理器中预留高速缓存的第一部分。收件箱与由处理器执行的第一个线程相关联。该方法还包括从第二线程接收分组，其中分组包括接入请求。该方法还包括使用收件箱控制电路来收件箱来处理接收到的分组并且确定是否授予包含在分组中的接入请求。

35. 发明申请

US20080028154A1 Method and Apparatus for Memory Utilization 有权
标题翻译：记忆利用方法和装置
公开(公告)号：US20080028154A1
公开(公告)日：2008-01-31
申请号：US11567874
申请日：2006-12-07
申请人： Russell Dean Hoover , Jon K. Kriegel , Eric Oliver Mejdrich , Robert Allen Shearer
发明人： Russell Dean Hoover , Jon K. Kriegel , Eric Oliver Mejdrich , Robert Allen Shearer
IPC分类号： G06F12/00
CPC分类号： G06T15/50 , G06T15/06
摘要： One embodiment of the invention provides a method and apparatus for utilizing memory. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from a second thread, wherein the packet includes an access request. The method further includes using inbox control circuitry for the inbox to process the received packet and determine whether to grant the access request included in the packet.
摘要翻译：本发明的一个实施例提供一种利用存储器的方法和装置。该方法包括在收件箱的处理器中预留高速缓存的第一部分。收件箱与由处理器执行的第一个线程相关联。该方法还包括从第二线程接收分组，其中分组包括接入请求。该方法还包括使用收件箱控制电路来收件箱来处理接收到的分组并且确定是否授予包含在分组中的接入请求。

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