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31. 发明授权

US08193630B2 System and method of silicon switched power delivery using a package 有权
标题翻译：使用封装的硅开关电源传输的系统和方法
公开(公告)号：US08193630B2
公开(公告)日：2012-06-05
申请号：US13006709
申请日：2011-01-14
申请人： Lew G. Chua-Eoan , Thomas R. Toms , Boris Dimitrov Andreev , Justin Joseph Rosen Gagne , Chunlei Shi
发明人： Lew G. Chua-Eoan , Thomas R. Toms , Boris Dimitrov Andreev , Justin Joseph Rosen Gagne , Chunlei Shi
IPC分类号： H01L23/52
CPC分类号： H03K17/223 , H01L2924/0002 , H01L2924/00
摘要： In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first package-substrate connection, a second package-substrate connection, and metallization coupling the first package-substrate connection to the second package-substrate connection. The substrate is coupled to the package via the first package-substrate connection and the second package-substrate connection. The substrate includes a plurality of power domains and a power control unit. The second package-substrate connection of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first package-substrate connection of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package.
摘要翻译：在一个具体实施例中，集成电路包括电气和物理耦合到封装的封装和衬底。封装包括第一封装 - 衬底连接，第二封装 - 衬底连接以及将第一封装 - 衬底连接耦合到第二封装 - 衬底连接的金属化。衬底经由第一封装 - 衬底连接和第二封装 - 衬底连接耦合到封装。基板包括多个电力域和功率控制单元。封装的第二封装 - 衬底连接耦合到多个电源域的特定电源域。功率控制单元包括逻辑和开关，其中开关包括耦合到电压源端子的第一端子，耦合到逻辑电路的控制端子和耦合到封装的第一封装 - 衬底连接的第二端子。逻辑选择性地激活开关以通过封装的金属化分配功率到特定的功率域。

32. 发明授权

US08184414B2 Method and apparatus for forming I/O clusters in integrated circuits 有权
标题翻译：用于在集成电路中形成I / O簇的方法和装置
公开(公告)号：US08184414B2
公开(公告)日：2012-05-22
申请号：US12182454
申请日：2008-07-30
申请人： Reza Jalilizeinali , Sreeker Dundigal , Vivek Mohan , Thomas R. Toms
发明人： Reza Jalilizeinali , Sreeker Dundigal , Vivek Mohan , Thomas R. Toms
IPC分类号： H02H9/00
CPC分类号： H01L27/0921 , H01L21/823871 , H01L23/50 , H01L24/02 , H01L27/0207 , H01L27/0266 , H01L2924/14 , H01L2924/3025 , H03K19/00315 , Y10T29/49117
摘要： A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.
摘要翻译：第一I / O焊盘具有设置在第一I / O焊盘的第一端的第一型晶体管。第二I / O焊盘具有设置在第二I / O焊盘的第一端的另一第一型晶体管。第一I / O焊盘的第一端邻接第二I / O焊盘的第一端，因此第一型晶体管与另一第一型晶体管相邻。

33. 发明授权

US08143952B2 Three dimensional inductor and transformer 有权
标题翻译：三维电感和变压器
公开(公告)号：US08143952B2
公开(公告)日：2012-03-27
申请号：US12576033
申请日：2009-10-08
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
IPC分类号： H03F3/14
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.
摘要翻译：公开了三维片上电感器，变压器和射频放大器。射频放大器包括一对变压器和晶体管。变压器包括至少两个电感耦合电感器。电感器包括第一金属层的多个段，第二金属层的多个段，第一电感器输入端，第二电感器输入端和耦合第一金属层的多个段的多个穿通硅通孔以及第二金属层的多个段，以在第一电感器输入端和第二电感器输入端之间形成连续的，不相交的路径。电感器可以具有对称或不对称的几何形状。第一金属层可以是芯片的后端部分中的金属层。第二金属层可以位于芯片的再分布设计层中。

34. 发明申请

US20110193212A1 Systems and Methods Providing Arrangements of Vias 审中-公开
标题翻译：系统和方法提供安排通风口
公开(公告)号：US20110193212A1
公开(公告)日：2011-08-11
申请号：US12701642
申请日：2010-02-08
申请人： Shiqun Gu , Matthew Michael Nowak , Durodami J. Lisk , Thomas R. Toms , Urmi Ray , Jungwon Suh , Arvind Chandrasekaran
发明人： Shiqun Gu , Matthew Michael Nowak , Durodami J. Lisk , Thomas R. Toms , Urmi Ray , Jungwon Suh , Arvind Chandrasekaran
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5286 , H01L23/3677 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05093 , H01L2224/13009 , H01L2224/13025 , H01L2224/13028 , H01L2224/131 , H01L2224/14505 , H01L2224/16145 , H01L2224/16146 , H01L2224/17517 , H01L2224/48091 , H01L2224/48227 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values.
摘要翻译：半导体芯片包括电连接阵列和将半导体芯片中的至少一个电路耦合到电接触阵列的多个通孔。电触点阵列的电触点中的第一个耦合到N个通孔，并且电触点阵列的电触点中的第二个耦合到M个通孔。 M和N是不同值的正整数。

35. 发明申请

US20110111705A1 System and Method of Silicon Switched Power Delivery Using a Package 有权
标题翻译：使用封装的硅开关电源的系统和方法
公开(公告)号：US20110111705A1
公开(公告)日：2011-05-12
申请号：US13006709
申请日：2011-01-14
申请人： Lew G. Chua-Eoan , Thomas R. Toms , Boris Dimitrov Andreev , Justin Joseph Rosen Gagne , Chunlei Shi
发明人： Lew G. Chua-Eoan , Thomas R. Toms , Boris Dimitrov Andreev , Justin Joseph Rosen Gagne , Chunlei Shi
IPC分类号： G05F1/10 , H04W52/00
CPC分类号： H03K17/223 , H01L2924/0002 , H01L2924/00
摘要： In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first package-substrate connection, a second package-substrate connection, and metallization coupling the first package-substrate connection to the second package-substrate connection. The substrate is coupled to the package via the first package-substrate connection and the second package-substrate connection. The substrate includes a plurality of power domains and a power control unit. The second package-substrate connection of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first package-substrate connection of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package.
摘要翻译：在一个具体实施例中，集成电路包括电气和物理耦合到封装的封装和衬底。封装包括第一封装 - 衬底连接，第二封装 - 衬底连接以及将第一封装 - 衬底连接耦合到第二封装 - 衬底连接的金属化。衬底经由第一封装 - 衬底连接和第二封装 - 衬底连接耦合到封装。基板包括多个电力域和功率控制单元。封装的第二封装 - 衬底连接耦合到多个电源域的特定电源域。功率控制单元包括逻辑和开关，其中开关包括耦合到电压源端子的第一端子，耦合到逻辑电路的控制端子和耦合到封装的第一封装 - 衬底连接的第二端子。逻辑选择性地激活开关以通过封装的金属化分配功率到特定的功率域。

36. 发明授权

US07904770B2 Testing circuit split between tiers of through silicon stacking chips 有权
标题翻译：测试电路分层穿过硅堆叠芯片
公开(公告)号：US07904770B2
公开(公告)日：2011-03-08
申请号：US12206977
申请日：2008-09-09
申请人： Thomas R. Toms
发明人： Thomas R. Toms
IPC分类号： G01R31/28 , G01R31/02 , H01L23/58 , H01L23/12 , H01L23/34 , H01L23/48
CPC分类号： G01R31/318511 , H01L25/0657 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/00
摘要： A method of testing a die having a non-testable circuit, where the non-testable circuit is logically incomplete and forms part of a logically complete multiple tier circuit. The method includes reconfiguring a tier-to-tier input point or tier-to-tier output point associated with a primary path of the non-testable circuit to create a logically complete secondary path for the tier-to-tier point such that the non-testable circuit can be tested. Testable dies and methods of preparing such dies are also provided.
摘要翻译：一种测试具有不可测试电路的芯片的方法，其中不可测试的电路在逻辑上不完整并且形成逻辑完整的多层电路的一部分。该方法包括重新配置与不可测试电路的主路径相关联的层到层输入点或层到层输出点，以创建用于层到层点的逻辑上完整的辅助路径，使得非 - 可测试电路可以测试。还提供了可测试的模具和制备这种模具的方法。

37. 发明授权

US07902654B2 System and method of silicon switched power delivery using a package 有权
标题翻译：使用封装的硅开关电源传输的系统和方法
公开(公告)号：US07902654B2
公开(公告)日：2011-03-08
申请号：US11431790
申请日：2006-05-10
申请人： Lew G. Choa-Eoan , Thomas R. Toms , Boris Dimitrov Andreev , Justin Joseph Rosen Gagne , Chunlei Shi
发明人： Lew G. Choa-Eoan , Thomas R. Toms , Boris Dimitrov Andreev , Justin Joseph Rosen Gagne , Chunlei Shi
IPC分类号： H01L23/52
CPC分类号： H03K17/223 , H01L2924/0002 , H01L2924/00
摘要： In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first pin, a second pin, and metallization coupling the first pin to the second pin. The substrate is coupled to the package via the first pin and the second pin. The substrate includes a plurality of power domains and a power control unit. The second pin of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first pin of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package.
摘要翻译：在一个具体实施例中，集成电路包括电气和物理耦合到封装的封装和衬底。封装包括第一引脚，第二引脚和将第一引脚耦合到第二引脚的金属化。衬底经由第一引脚和第二引脚耦合到封装。基板包括多个电力域和功率控制单元。封装的第二引脚耦合到多个电源域的特定电源域。功率控制单元包括逻辑和开关，其中开关包括耦合到电压源端子的第一端子，耦合到逻辑电路的控制端子和耦合到封装的第一引脚的第二端子。逻辑选择性地激活开关以通过封装的金属化分配功率到特定的功率域。

38. 发明申请

US20100206370A1 Photovoltaic Cell Efficiency Using Through Silicon Vias 审中-公开
标题翻译：使用硅通孔的光伏电池效率
公开(公告)号：US20100206370A1
公开(公告)日：2010-08-19
申请号：US12372778
申请日：2009-02-18
申请人： Thomas R. Toms , Shiqun Gu
发明人： Thomas R. Toms , Shiqun Gu
IPC分类号： H01L31/00
CPC分类号： H01L31/022425 , H01L31/02168 , H01L31/022466 , H01L31/022475 , Y02E10/52 , Y02E10/547
摘要： A photovoltaic cell includes a photovoltaic layer having a first node and a second node. A first conductive layer is electrically coupled to the second node of the photovoltaic layer so the first conductive layer does not block light from the photovoltaic layer. A second conductive layer is adjacent to but electrically insulated from the first conductive layer, so the second conductive layer is positioned where it does not block light from the photovoltaic layer. At least one through silicon via is electrically coupled to the first node of the photovoltaic layer and the second conductive layer, but is electrically insulated from at least a portion of the photovoltaic layer and the first conductive layer.
摘要翻译：光伏电池包括具有第一节点和第二节点的光伏层。第一导电层电耦合到光伏层的第二节点，使得第一导电层不阻挡来自光伏层的光。第二导电层与第一导电层相邻但是电绝缘，因此第二导电层被定位在不阻挡来自光伏层的光的地方。至少一个通硅通孔电耦合到光伏层和第二导电层的第一节点，但与光电转换层和第一导电层的至少一部分电绝缘。

39. 发明申请

US20100091475A1 Electrostatic Discharge (ESD) Shielding For Stacked ICs 审中-公开
标题翻译：用于堆叠IC的静电放电（ESD）屏蔽
公开(公告)号：US20100091475A1
公开(公告)日：2010-04-15
申请号：US12251802
申请日：2008-10-15
申请人： Thomas R. Toms , Reza Jalilizeinali , Shiqun Gu
发明人： Thomas R. Toms , Reza Jalilizeinali , Shiqun Gu
IPC分类号： H05K9/00 , H01L21/00
CPC分类号： H01L23/60 , H01L25/0657 , H01L2224/274 , H01L2924/01055 , H01L2924/12044
摘要： An unassembled stacked IC device includes an unassembled tier. The unassembled stacked IC device also includes a first unpatterned layer on the unassembled tier. The first unpatterned layer protects the unassembled tier from ESD events.
摘要翻译：未组装的堆叠式IC器件包括未组装的层。未组装的堆叠IC器件还包括未组装层上的第一未图案层。第一个无图案层保护未组装的层免受ESD事件的影响。

40. 发明申请

US20090321909A1 Active Thermal Control for Stacked IC Devices 有权
标题翻译：堆叠IC器件的主动热控制
公开(公告)号：US20090321909A1
公开(公告)日：2009-12-31
申请号：US12163029
申请日：2008-06-27
申请人： Shiqun Gu , Matthew Nowak , Thomas R. Toms
发明人： Shiqun Gu , Matthew Nowak , Thomas R. Toms
IPC分类号： H01L23/38
CPC分类号： H05K7/20 , H01L23/38 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06589 , H01L2924/00014 , H01L2224/05599
摘要： Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.
摘要翻译：可以通过在堆叠的IC器件内构造一个或多个有源温度控制器件来提高层叠IC器件中的导热性。在一个实施例中，控制装置是诸如珀耳帖装置之类的热电（TE）装置。然后可根据需要选择性地控制TE器件去除或加热，以将堆叠的IC器件保持在规定的温度范围内。活性温度控制元件可以是在堆叠的IC器件中产生的P-N结，并且可以根据需要用于横向和/或垂直地移动热量。

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