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31. 发明申请

US20150223022A1 GEOFENCING 有权
标题翻译：地理学
公开(公告)号：US20150223022A1
公开(公告)日：2015-08-06
申请号：US14126172
申请日：2013-06-28
申请人： Arvind KUMAR , Adam ECKELS
发明人： Arvind Kumar , Adam Eckels
IPC分类号： H04W4/02
CPC分类号： H04W4/021 , G08B21/22
摘要： In one embodiment an apparatus comprises logic, at least partially including hardware logic, configured to establish a geographic reference point, define one or more geofences relative to the geographic reference point determine, baaed on an input from at least one inertial sensor, a location of the apparatus relative to the geographic reference point, and generate a warning signal in response to a determination that the location of the apparatus is outside the one or snore geofences. Other embodiments may be described.
摘要翻译：在一个实施例中，一种装置包括至少部分地包括硬件逻辑的逻辑，其被配置为建立地理参考点，相对于地理参考点定义一个或多个地理位置确定来自至少一个惯性传感器的输入上的位置，所述设备相对于所述地理参考点，并且响应于所述设备的位置在所述一个或打鼾地理围栏之外的确定而产生警告信号。可以描述其他实施例。

32. 发明授权

US08839356B2 Methods and apparatuses for processing wake events of communication networks 有权
标题翻译：处理通信网络唤醒事件的方法和装置
公开(公告)号：US08839356B2
公开(公告)日：2014-09-16
申请号：US12006150
申请日：2007-12-31
申请人： Michael A. Rothman , Arvind Kumar , Vincent J. Zimmer , Patrick G. Kutch , Omer Levy
发明人： Michael A. Rothman , Arvind Kumar , Vincent J. Zimmer , Patrick G. Kutch , Omer Levy
IPC分类号： G06F1/00 , G06F7/04 , G06F17/30 , H04L9/32 , H04L29/06 , G06F21/85
CPC分类号： H04L63/08 , G06F1/3209 , G06F21/85 , H04L12/12 , H04L63/083 , Y02D50/40
摘要： Methods, apparatuses, and computer program products that respond to wake events of communication networks are disclosed. One or more embodiments comprise setting a wake password of a computing device, such as a notebook computer or a server. Some of the embodiments comprise receiving a wake request from a communications network, establishing a secure communication session, and setting the wake password with the secure communication session. Some embodiments comprise an apparatus having a network controller to allow a platform to communicate via a communications network, non-volatile memory that stores a wake password, and a management controller that may communicate with a management console via a secure communication session to update the wake password. One or more embodiments the network controller may wake management hardware and/or wake the management controller while keeping one or more of the devices in the power conservation mode.
摘要翻译：公开了响应通信网络的唤醒事件的方法，设备和计算机程序产品。一个或多个实施例包括设置诸如笔记本计算机或服务器之类的计算设备的唤醒密码。一些实施例包括从通信网络接收唤醒请求，建立安全通信会话，以及利用安全通信会话设置唤醒密码。一些实施例包括具有网络控制器的设备，其允许平台经由通信网络进行通信，存储唤醒密码的非易失性存储器以及可以经由安全通信会话与管理控制台通信以更新唤醒的管理控制器密码。一个或多个实施例，网络控制器可以在保持一个或多个设备处于功率节省模式的同时唤醒管理硬件和/或唤醒管理控制器。

33. 发明授权

US08680623B2 Techniques for enabling multiple Vt devices using high-K metal gate stacks 有权
标题翻译：使用高K金属栅极堆叠实现多个Vt器件的技术
公开(公告)号：US08680623B2
公开(公告)日：2014-03-25
申请号：US13433815
申请日：2012-03-29
申请人： Martin M. Frank , Arvind Kumar , Vijay Narayanan , Vamsi K. Paruchuri , Jeffrey Sleight
发明人： Martin M. Frank , Arvind Kumar , Vijay Narayanan , Vamsi K. Paruchuri , Jeffrey Sleight
IPC分类号： H01L21/8244 , H01L21/70
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108
摘要： Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.
摘要翻译：提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压，SRAM nFET和SRAM pFET。

34. 发明申请

US20130344677A1 SHALLOW TRENCH ISOLATION STRUCTURES 有权
公开(公告)号：US20130344677A1
公开(公告)日：2013-12-26
申请号：US13531780
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

35. 发明申请

US20130341754A1 SHALLOW TRENCH ISOLATION STRUCTURES 有权
公开(公告)号：US20130341754A1
公开(公告)日：2013-12-26
申请号：US13531654
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

36. 发明申请

US20130328124A1 GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL 失效
标题翻译：用于消除从盖拆卸中的RIE损伤的栅极二极管结构
公开(公告)号：US20130328124A1
公开(公告)日：2013-12-12
申请号：US13489537
申请日：2012-06-06
申请人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
发明人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
IPC分类号： H01L27/06 , H01L21/8238
CPC分类号： H01L21/8238 , H01L21/265 , H01L21/77 , H01L21/823835 , H01L27/0629 , H01L27/1203 , H01L29/42364 , H01L29/7391 , H01L29/861
摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.
摘要翻译：一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

37. 发明授权

US08482075B2 Structure and method for manufacturing asymmetric devices 有权
标题翻译：用于制造不对称装置的结构和方法
公开(公告)号：US08482075B2
公开(公告)日：2013-07-09
申请号：US13468270
申请日：2012-05-10
申请人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert Robison
发明人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert Robison
IPC分类号： H01L21/70
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/66545 , H01L29/66659
摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.
摘要翻译：在基板上形成多个栅极结构。每个栅极结构包括第一栅极电极和源极和漏极区域。从每个栅极结构去除第一栅电极。施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。去除第一光致抗蚀剂。施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。去除第二光致抗蚀剂。在每个栅极结构中形成替代栅电极。

38. 发明授权

US08343781B2 Electrical mask inspection 失效
标题翻译：电气面罩检查
公开(公告)号：US08343781B2
公开(公告)日：2013-01-01
申请号：US12886612
申请日：2010-09-21
申请人： Arvind Kumar , Anthony I-Chih Chou , Shreesh Narasimha
发明人： Arvind Kumar , Anthony I-Chih Chou , Shreesh Narasimha
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L23/544 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.
摘要翻译：公开了一种用于电气掩模检查的装置和方法。在两个金属层和通孔层之间形成扫描链。三层之一是被测功能层，另外两层是测试层。使用扫描链的电阻测量来确定在包括扫描链的通孔或金属段之一内是否存在潜在缺陷。

39. 发明申请

US20120192000A1 METHOD AND APPARATUS FOR COST AND POWER EFFICIENT, SCALABLE OPERATING SYSTEM INDEPENDENT SERVICES 有权
标题翻译：成本和功率有效的可扩展操作系统独立服务的方法和装置
公开(公告)号：US20120192000A1
公开(公告)日：2012-07-26
申请号：US13436835
申请日：2012-03-30
申请人： Arvind Kumar , Per Hammarlund , Glenn Hinton , Johan G. Van De Groenendaal
发明人： Arvind Kumar , Per Hammarlund , Glenn Hinton , Johan G. Van De Groenendaal
IPC分类号： G06F1/00
CPC分类号： G06F1/3287 , G06F1/3209 , Y02D10/171
摘要： A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.
摘要翻译：提供了低成本，低功耗的可扩展架构，以允许在所有系统电源状态期间远程管理计算机系统。在最低功率状态下，功率仅适用于检查网络分组所需的最小逻辑。将电力短时间施加到执行子系统，并且被选择用于处理所接收的服务请求的处理的多个核心中的一个。在处理接收到的服务请求之后，计算机系统返回到最低功率状态。

40. 发明申请

US20120068174A1 ELECTRICAL MASK INSPECTION 失效
标题翻译：电磁屏蔽检查
公开(公告)号：US20120068174A1
公开(公告)日：2012-03-22
申请号：US12886612
申请日：2010-09-21
申请人： Arvind Kumar , Anthony I-Chih Chou , Shreesh Narasimha
发明人： Arvind Kumar , Anthony I-Chih Chou , Shreesh Narasimha
IPC分类号： H01L23/522 , H01L21/66 , H01L21/768
CPC分类号： H01L23/544 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.
摘要翻译：公开了一种用于电气掩模检查的装置和方法。在两个金属层和通孔层之间形成扫描链。三层之一是被测功能层，另外两层是测试层。使用扫描链的电阻测量来确定在包括扫描链的通孔或金属段之一内是否存在潜在缺陷。

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