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31. 发明授权

US07871916B2 Transistor gate electrode having conductor material layer 有权
公开(公告)号：US07871916B2
公开(公告)日：2011-01-18
申请号：US12553033
申请日：2009-09-02
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

32. 发明申请

US20100102401A1 Semiconductor transistor having a stressed channel 审中-公开
公开(公告)号：US20100102401A1
公开(公告)日：2010-04-29
申请号：US12655349
申请日：2009-12-29
申请人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
发明人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7842
摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

33. 发明申请

US20100044754A1 STRAINED TRANSISTOR INTEGRATION FOR CMOS 有权
标题翻译： CMOS的应变晶体管集成
公开(公告)号：US20100044754A1
公开(公告)日：2010-02-25
申请号：US12609711
申请日：2009-10-30
申请人： Boyan Boyanov , Anand Murthy , Brian S. Doyle , Robert Chau
发明人： Boyan Boyanov , Anand Murthy , Brian S. Doyle , Robert Chau
IPC分类号： H01L29/78
CPC分类号： H01L29/7849 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L27/092 , H01L29/78
摘要： Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.
摘要翻译：本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

34. 发明申请

US20090152589A1 Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors 审中-公开
标题翻译：在三栅晶体管中提高单轴压缩应力的系统和方法
公开(公告)号：US20090152589A1
公开(公告)日：2009-06-18
申请号：US11958275
申请日：2007-12-17
申请人： Titash Rakshit , Martin D. Giles , Tahir Ghani , Anand Murthy , Stephen M. Cea
发明人： Titash Rakshit , Martin D. Giles , Tahir Ghani , Anand Murthy , Stephen M. Cea
IPC分类号： H01L29/778 , H01L21/8234
CPC分类号： H01L21/26506 , H01L21/823437 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the semiconductor bodies, wherein the common source region is coupled to all of the at least two semiconductor bodies, a common drain region formed on another end of the semiconductor bodies, wherein the common drain region is coupled to all of the at least two semiconductor bodies, and a common gate electrode formed over the at least two semiconductor bodies, wherein the common gate electrode provides a gate electrode for each of the at least two semiconductor bodies and wherein the common gate electrode has a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies.
摘要翻译：增加三栅极晶体管的沟道区上的单轴压应力的晶体管结构包括形成在衬底上的至少两个半导体本体，每个半导体本体具有一对横向相对的侧壁和顶表面，共同源极区形成在所述半导体主体的一端，其中所述公共源极区域耦合到所述至少两个半导体主体中的所有半导体主体，形成在所述半导体主体的另一端上的公共漏极区域，其中，所述公共漏极区域至少与所述半导体主体两个半导体主体和形成在所述至少两个半导体主体上的公共栅电极，其中所述公共栅电极为所述至少两个半导体主体中的每一个提供栅电极，并且其中所述公共栅极具有一对横向相对的侧壁，基本上垂直于半导体主体的侧壁。

35. 发明授权

US07422971B2 Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby 有权
标题翻译：包含EPI硅尖端和由此制成的制品的超薄体SOI器件的工艺
公开(公告)号：US07422971B2
公开(公告)日：2008-09-09
申请号：US11204418
申请日：2005-08-15
申请人： Anand Murthy , Brian Doyle , Jack Kavalieros , Robert Chau
发明人： Anand Murthy , Brian Doyle , Jack Kavalieros , Robert Chau
IPC分类号： H01L21/00
CPC分类号： H01L29/41733 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/66772 , H01L29/78618
摘要： The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.
摘要翻译：本发明涉及一种晶体管，其包括超薄体外延层，该超薄体外延层与具有由晶体管的栅极堆叠下方的底切指定的沟道的沟道形成嵌入的结。本发明还涉及一种形成晶体管的方法和涉及晶体管的系统。

36. 发明申请

US20070281411A1 Formation of strain-inducing films 失效
标题翻译：应变诱导膜的形成
公开(公告)号：US20070281411A1
公开(公告)日：2007-12-06
申请号：US11448247
申请日：2006-06-06
申请人： Anand Murthy , Glenn Glass , Michael L. Hattendorf
发明人： Anand Murthy , Glenn Glass , Michael L. Hattendorf
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02529 , H01L21/0262 , H01L21/02642 , H01L21/02664 , H01L21/324 , H01L29/6659 , H01L29/66628 , H01L29/66636
摘要： A method to form a strain-inducing three-component epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is formed by formed by a multiple deposition/etch step sequence, followed by an amorphizing dopant impurity-implant and, finally, a kinetically-driven crystallization process. In one embodiment, the charge-neutral lattice-substitution atoms are smaller and present in greater concentration than the charge-carrier dopant impurity atoms.
摘要翻译：描述形成应变诱导三组分外延膜的方法。在一个实施例中，通过多次沉积/蚀刻步骤顺序形成应变诱导外延膜，接着是非晶化掺杂剂杂质注入，最后是动力学驱动的结晶过程。在一个实施方案中，电荷 - 中性晶格取代原子更小并且以比电荷 - 载流子掺杂剂杂质原子更高的浓度存在。

37. 发明授权

US07223679B2 Transistor gate electrode having conductor material layer 有权
公开(公告)号：US07223679B2
公开(公告)日：2007-05-29
申请号：US10745978
申请日：2003-12-24
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L21/4763
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

38. 发明申请

US20060220153A1 Method of fabricating a field effect transistor structure with abrupt source/drain junctions 有权
标题翻译：制造具有突然的源极/漏极结的场效应晶体管结构的方法
公开(公告)号：US20060220153A1
公开(公告)日：2006-10-05
申请号：US11437569
申请日：2006-05-19
申请人： Anand Murthy , Robert Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
发明人： Anand Murthy , Robert Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
IPC分类号： H01L29/76
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/0262 , H01L21/2022 , H01L29/0646 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66477 , H01L29/66492 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.
摘要翻译：体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。凹部包括在栅极结构的一部分下面的横向延伸的区域。这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。替代实施例可以用单导电类型的后填充凹槽来实现。

39. 发明申请

US20060131665A1 Method for forming an integrated circuit 有权
标题翻译：集成电路形成方法
公开(公告)号：US20060131665A1
公开(公告)日：2006-06-22
申请号：US11336160
申请日：2006-01-20
申请人： Anand Murthy , Glenn Glass , Andrew Westmeyer , Michael Hattendorf , Tahir Ghani
发明人： Anand Murthy , Glenn Glass , Andrew Westmeyer , Michael Hattendorf , Tahir Ghani
IPC分类号： H01L29/76
CPC分类号： H01L29/7834 , H01L29/665 , H01L29/66636
摘要： A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses via a selective epitaxial growth process. The epitaxial silicon is in-situ alloyed with substitutional carbon and in-situ doped with phosphorus. The silicon-carbon alloy generates a uniaxial tensile strain in the channel region between the source and drain, thereby increasing electron channel mobility and the transistor's drive current. The silicon-carbon alloy decreases external resistances by reducing contact resistance between source/drain and silicide regions and by reducing phosphorous diffusivity, thereby permitting closer placement of the transistor's source/drain and channel regions.
摘要翻译：描述了制造n-MOS半导体晶体管的方法。在与栅电极结构相邻的半导体衬底中形成凹部。硅通过选择性外延生长工艺嵌入凹槽中。外延硅与替代原位合金化并原位掺磷。硅碳合金在源极和漏极之间的沟道区域中产生单轴拉伸应变，从而增加电子通道迁移率和晶体管的驱动电流。硅碳合金通过降低源极/漏极和硅化物区域之间的接触电阻并减少磷扩散率来降低外部电阻，从而允许晶体管的源极/漏极和沟道区域更靠近放置。

40. 发明授权

US07064042B1 Self aligned compact bipolar junction transistor layout, and method of making same 失效
公开(公告)号：US07064042B1
公开(公告)日：2006-06-20
申请号：US10877749
申请日：2004-06-24
申请人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green , Anand Murthy
发明人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green , Anand Murthy
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/732
摘要： The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

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