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31. 发明授权

US08122405B2 Delay adjusting method and LSI that uses air-gap wiring 有权
标题翻译：延时调整方法和使用气隙接线的LSI
公开(公告)号：US08122405B2
公开(公告)日：2012-02-21
申请号：US12253469
申请日：2008-10-17
申请人： Takashi Matsumoto , Junji Noguchi , Takayuki Oshima
发明人： Takashi Matsumoto , Junji Noguchi , Takayuki Oshima
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method for manufacturing a semiconductor integrated circuit device which enables a timing optimization without giving additions to a manufacturing process and increasing cost and TAT. Existence of a timing constraint violation is determined, and when a timing constraint violation is detected, to dissolve the violation, a void formation inhibition zone is set up in a part or all of a spacing (inter-wiring spacing) between an optimization-target wiring which needs a further delay time of a signal and clock and an adjacent wiring adjacent to the optimization-target wiring having a spacing within a specified wiring spacing, and an insulating film is formed in a spacing (inter-wiring spacing) between the optimization-target wiring and the adjacent wiring in the void formation inhibition zone, and voids are formed in a spacing (inter-wiring spacing) between the optimization-target wiring and the adjacent wiring outside the void formation inhibition zone.
摘要翻译：提供一种制造半导体集成电路器件的方法，其能够进行定时优化，而不增加制造工艺并增加成本和TAT。确定定时约束违规的存在，并且当检测到定时约束违规时，为了解决违规，在优化目标之间的间隔（布线间距）的一部分或全部中建立空隙形成禁止区需要进一步延迟信号和时钟的延迟时间的布线以及与优选目标布线相邻的相邻布线，其间距在指定布线间距内，并且绝缘膜以优选的间隔（布线间距）形成在空隙形成抑制区域中的目标布线和相邻布线，并且在空隙形成抑制区外部的优化目标布线和相邻布线之间的间隔（布线间距）形成空隙。

32. 发明授权

US08053893B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08053893B2
公开(公告)日：2011-11-08
申请号：US12489006
申请日：2009-06-22
申请人： Junji Noguchi , Takayuki Oshima , Noriko Miura , Kensuke Ishikawa , Tomio Iwaskai , Kiyomi Katsuyama , Tatsuyuki Saito , Tsuyoshi Tamaru , Hizuru Yamaguchi
发明人： Junji Noguchi , Takayuki Oshima , Noriko Miura , Kensuke Ishikawa , Tomio Iwaskai , Kiyomi Katsuyama , Tatsuyuki Saito , Tsuyoshi Tamaru , Hizuru Yamaguchi
IPC分类号： H01L23/52
CPC分类号： H01L21/76811 , H01L21/314 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76813 , H01L21/76814 , H01L21/76822 , H01L21/76832 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76883 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
摘要翻译：提高了布线的可靠性，其中包括以铜为主要成分的主导电膜。在包括用作下层布线的布线的上表面的绝缘膜上形成由铜阻隔性优异的碳氮化硅膜形成的绝缘膜; 在绝缘膜上形成由与低介电常数材料膜具有优异粘合性的碳化硅膜形成的绝缘膜; 在绝缘膜上形成由作为层间绝缘膜的低介电常数材料形成的绝缘膜; 然后形成作为上层布线的布线。

33. 发明申请

US20110140275A1 Semiconductor device and manufacturing method of the same 有权
公开(公告)号：US20110140275A1
公开(公告)日：2011-06-16
申请号：US12929782
申请日：2011-02-15
申请人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
发明人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
IPC分类号： H01L23/532
CPC分类号： H01L21/7682 , H01L21/76811 , H01L21/76832 , H01L21/76834 , H01L21/76843
摘要： In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.

34. 发明授权

US06480518B1 Synthetic quartz glass member for use in ArF excimer laser lithography 有权
标题翻译：用于ArF准分子激光光刻的合成石英玻璃构件
公开(公告)号：US06480518B1
公开(公告)日：2002-11-12
申请号：US09517888
申请日：2000-03-03
申请人： Akira Fujinoki , Takayuki Oshima , Hiroyuki Nishimura , Yasuyuki Yaginuma
发明人： Akira Fujinoki , Takayuki Oshima , Hiroyuki Nishimura , Yasuyuki Yaginuma
IPC分类号： H01S322
CPC分类号： C03C3/06 , C03B19/1453 , C03B2201/07 , C03B2201/21 , C03C4/0085 , C03C23/002 , C03C2201/21 , C03C2201/50 , C03C2203/42 , C03C2203/50
摘要： A synthetic glass member for use in excimer laser lithography, having superior homogeneity, high transmittance for ArF excimer laser beams and an excellent resistance against lasers is made from high purity synthetic quartz glass, and it is characterized in that layered structures, striae in three directions and internal strains are thermally and mechanically removed, the distribution of refractive index (&Dgr;n) in a plane orthogonal to the optical axis is up to about 1×10−6, the distribution of refractive index (&Dgr;n) in a plane parallel to the optical axis is up to about 5×10−6, the birefringence is up to about 2 nm/cm, the hydrogen molecule concentration is at least about 2×1017 molecules/cm3, and the internal transmittance is at least about 99.8% at a wavelength of 193.4 nm.
摘要翻译：用于准分子激光光刻的合成玻璃构件，具有优异的均匀性，对ArF准分子激光束的高透射率和优异的抗激光性能由高纯度合成石英玻璃制成，其特征在于层状结构，沿三个方向并且内部应变被热和机械去除，在与光轴正交的平面中折射率（DELTAn）的分布高达约1×10 -6，平行于光轴的平面中的折射率分布（DELTAn）为高达约5×10 -6，双折射高达约2nm / cm，氢分子浓度为至少约2×10 17分子/ cm 3，内部透射率在193.4nm波长处为至少约99.8％。

35. 发明授权

US08431480B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US08431480B2
公开(公告)日：2013-04-30
申请号：US13243882
申请日：2011-09-23
申请人： Junji Noguchi , Takayuki Oshima , Noriko Miura , Kensuke Ishikawa , Tomio Iwaskai , Kiyomi Katsuyama , Tatsuyuki Saito , Tsuyoshi Tamaru , Hizuru Yamaguchi
发明人： Junji Noguchi , Takayuki Oshima , Noriko Miura , Kensuke Ishikawa , Tomio Iwaskai , Kiyomi Katsuyama , Tatsuyuki Saito , Tsuyoshi Tamaru , Hizuru Yamaguchi
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76811 , H01L21/314 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76813 , H01L21/76814 , H01L21/76822 , H01L21/76832 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76883 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

36. 发明授权

US08247902B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08247902B2
公开(公告)日：2012-08-21
申请号：US12929782
申请日：2011-02-15
申请人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
发明人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
IPC分类号： H01L23/48
CPC分类号： H01L21/7682 , H01L21/76811 , H01L21/76832 , H01L21/76834 , H01L21/76843
摘要： In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.
摘要翻译：在半导体器件中，铜互连之间的电容降低，并且同时提高绝缘击穿，并且通过包括以下步骤的制造方法采取不对准的对策：包括在绝缘膜上方形成包含铜作为主要成分的互连基板，形成绝缘膜和用于储存器图案的隔离绝缘膜，形成能够抑制或防止铜在互连的上表面和侧表面上以及在绝缘膜和绝缘膜上方形成的绝缘膜，形成绝缘膜的绝缘膜形成为使得相互连接的相对侧面上方的沉积速率大于其下方的沉积速率，以形成相邻互连之间的气隙，最后将绝缘膜平坦化膜层间CMP。

37. 发明申请

US20110024838A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110024838A1
公开(公告)日：2011-02-03
申请号：US12834787
申请日：2010-07-12
申请人： Keigo KITAZAWA , Junji Noguchi , Takayuki Oshima , Shinichiro Wada , Tomoyuki Miyoshi , Atsushi Itoh
发明人： Keigo KITAZAWA , Junji Noguchi , Takayuki Oshima , Shinichiro Wada , Tomoyuki Miyoshi , Atsushi Itoh
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0692 , H01L29/41758 , H01L29/42364 , H01L29/42372 , H01L29/4238
摘要： There is provided a high withstand voltage LDMOS which is a MOS transistor formed on a semiconductor substrate and isolated by a trench, and a source region of which is sandwiched by a drain region, in which the metal layer gate wire connected to the gate electrode is led out outside the trench so as to pass over a P-type drift layer.
摘要翻译：提供了一种高耐压LDMOS，其是形成在半导体衬底上并由沟槽隔离的MOS晶体管，其源极区域被漏极区夹在中，其中连接到栅电极的金属层栅极线为在沟槽外引出，以通过P型漂移层。

38. 发明申请

US20090256261A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090256261A1
公开(公告)日：2009-10-15
申请号：US12489006
申请日：2009-06-22
申请人： Junji Noguchi , Takayuki Oshima , Noriko Miura , Kensuke Ishikawa , Tomio Iwasaki , Kiyomi Katsuyama , Tatsuyuki Saito , Tsuyoshi Tamaru , Hizuru Yamaguchi
发明人： Junji Noguchi , Takayuki Oshima , Noriko Miura , Kensuke Ishikawa , Tomio Iwasaki , Kiyomi Katsuyama , Tatsuyuki Saito , Tsuyoshi Tamaru , Hizuru Yamaguchi
IPC分类号： H01L23/522
CPC分类号： H01L21/76811 , H01L21/314 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76813 , H01L21/76814 , H01L21/76822 , H01L21/76832 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76883 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
摘要翻译：提高了布线的可靠性，其中包括以铜为主要成分的主导电膜。在包括用作下层布线的布线的上表面的绝缘膜上形成由铜阻隔性优异的碳氮化硅膜形成的绝缘膜; 在绝缘膜上形成由与低介电常数材料膜具有优异粘合性的碳化硅膜形成的绝缘膜; 在绝缘膜上形成由作为层间绝缘膜的低介电常数材料形成的绝缘膜; 然后形成作为上层布线的布线。

39. 发明授权

US07111477B2 Production method of optical synthetic quartz glass, optical synthetic quartz glass, and annealing furnace 有权
公开(公告)号：US07111477B2
公开(公告)日：2006-09-26
申请号：US10320338
申请日：2002-12-16
申请人： Takayuki Oshima , Akira Fujinoki
发明人： Takayuki Oshima , Akira Fujinoki
IPC分类号： C03B25/00 , C03B20/00 , C03B25/02
CPC分类号： C03C3/06 , C03B19/1453 , C03B32/00 , Y02P40/57
摘要： An object is to provide a method for producing an optical synthetic quartz glass and an optical synthetic glass, having a birefringence of lower than 0.5 nm/cm and having favorable refractive index distribution, yet without lowering the productivity, as well as to provide an annealing furnace suitably used in practicing said method. In a step of raising the temperature of a columnar optical synthetic quartz glass preform to a temperature of from 800° C. to 1200° C., and after keeping for a definite time, lowering the temperature, the temperature is lowered with a temperature difference of from 1 to 20° C. between the temperature of the light transmitting surface of the optical synthetic quartz glass preform and the temperature of the outer peripheral side surface of the optical synthetic quartz glass preform at temperature-lowering rates of from 2 to 50° C./hour, respectively.

40. 发明申请

US20120270390A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120270390A1
公开(公告)日：2012-10-25
申请号：US13541229
申请日：2012-07-03
申请人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
发明人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/76811 , H01L21/76832 , H01L21/76834 , H01L21/76843
摘要： In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.
摘要翻译：在半导体器件中，铜互连之间的电容降低，并且同时提高绝缘击穿，并且通过包括以下步骤的制造方法采取不对准的对策：包括在绝缘膜上方形成包含铜作为主要成分的互连基板，形成绝缘膜和用于储存器图案的隔离绝缘膜，形成能够抑制或防止铜在互连的上表面和侧表面上以及在绝缘膜和绝缘膜上方形成的绝缘膜，形成绝缘膜的绝缘膜形成为使得相互连接的相对侧面上方的沉积速率大于其下方的沉积速率，以形成相邻互连之间的气隙，最后将绝缘膜平坦化膜层间CMP。

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