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31. 发明授权

US4520441A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US4520441A
公开(公告)日：1985-05-28
申请号：US329949
申请日：1981-12-11
申请人： Tadaaki Bandoh , Hidekazu Matsumoto , Yasushi Fukunaga , Ryosei Hiraoka , Jushi Ide , Tetsuya Kawakami
发明人： Tadaaki Bandoh , Hidekazu Matsumoto , Yasushi Fukunaga , Ryosei Hiraoka , Jushi Ide , Tetsuya Kawakami
IPC分类号： G06F12/08 , G06F12/10 , G06F13/00
CPC分类号： G06F12/1027 , G06F12/0866
摘要： A data processing system for supporting a virtual memory is disclosed. Prior to the start of main memory write operation, a processor checks to see if a store buffer has a vacant area to store data to be written into a main memory to execute a current instruction. If a page fault occurs during the main memory write operation, the processor continues to store the subsequent write data for the current instruction and the corresponding virtual or logical addresses in the store buffer to complete execution of the current instruction.
摘要翻译：公开了一种用于支持虚拟存储器的数据处理系统。在主存储器写入操作开始之前，处理器检查存储缓冲器是否具有空闲区域以存储要写入主存储器中的数据以执行当前指令。如果在主存储器写入操作期间发生页错误，则处理器继续存储当前指令的后续写入数据和存储缓冲器中的相应虚拟或逻辑地址，以完成当前指令的执行。

32. 发明授权

US4365311A Control of instruction pipeline in data processing system 失效
标题翻译：控制数据处理系统中的指令流水线
公开(公告)号：US4365311A
公开(公告)日：1982-12-21
申请号：US938346
申请日：1978-08-31
申请人： Yasushi Fukunaga , Tadaaki Bandoh
发明人： Yasushi Fukunaga , Tadaaki Bandoh
IPC分类号： G06F9/30 , G06F9/38 , G06F9/28
CPC分类号： G06F9/3869
摘要： In a data processing system having an instruction pipeline in which each instruction is allotted for execution, part by part, to segments provided in the instruction pipeline so that the first segment executes a part of one instruction allotted thereto, while the successive segments execute respective parts of the preceding instructions allotted thereto, a control of the instruction pipeline is arranged to provide the segments with individual reference clock signals whose timings are determined separately depending on the capacity of each segment for execution of the allotted part of each instruction and also variable depending on the actual condition of the system in execution of each instruction.
摘要翻译：在具有指令流水线的数据处理系统中，其中每个指令被分配用于执行，以逐步地分配到指令流水线中提供的段，使得第一段执行分配给其的一个指令的一部分，而连续的段执行相应的部分指定流水线的控制被布置成为段提供各自的参考时钟信号，其中定时根据用于执行每个指令的分配部分的每个段的容量分别确定，并且还取决于系统执行每条指令的实际情况。

33. 发明授权

US4896258A Data processor provided with instructions which refer to both tagged and tagless data 失效
标题翻译：数据处理器提供有指示标签和无标签数据的指令
公开(公告)号：US4896258A
公开(公告)日：1990-01-23
申请号：US881407
申请日：1986-07-02
申请人： Shinichiro Yamaguchi , Hidekazu Matsumoto , Tadaaki Bandoh , Hiroaki Nakanishi , Kenzi Hirose , Takao Kobayashi , Yoshihiro Miyazaki
发明人： Shinichiro Yamaguchi , Hidekazu Matsumoto , Tadaaki Bandoh , Hiroaki Nakanishi , Kenzi Hirose , Takao Kobayashi , Yoshihiro Miyazaki
IPC分类号： G06F9/30 , G06F9/318 , G06F9/44
CPC分类号： G06F9/30181 , G06F9/30061 , G06F9/30145 , G06F9/30167 , G06F9/30192 , G06F9/3557 , G06F9/4438
摘要： A data processor for execution of tagged data and tagless data has a decoder for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part for extracting the tag part from data on a data bus, a plurality of tag part storing registers for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.

34. 发明授权

US4296468A Address conversion unit for data processing system 失效
标题翻译：数据处理系统地址转换单元
公开(公告)号：US4296468A
公开(公告)日：1981-10-20
申请号：US945396
申请日：1978-09-25
申请人： Tadaaki Bandoh , Yasushi Fukunaga
发明人： Tadaaki Bandoh , Yasushi Fukunaga
IPC分类号： G06F9/34 , G06F12/02 , G06F9/20
CPC分类号： G06F12/0292
摘要： An address conversion method and unit for a data processing system is disclosed which converts logical addresses into physical addresses representative of plural addressable storage locations. Each instruction includes a portion indicative of a first or second kind of instruction. In the case where an instruction is of the first kind, the content of a register in a first base register arrangement specified by the instruction is added with an address part of the instruction to produce a logical address. In the case where an instruction is of the second kind, on the other hand, the content of a register in a second base register arrangement specified by the instruction different from the first base register arrangement is juxtaposed with an address part of the instruction to produce a logical address.
摘要翻译：公开了一种用于数据处理系统的地址转换方法和单元，其将逻辑地址转换为表示多个可寻址存储位置的物理地址。每个指令包括表示第一种或第二类指令的部分。在指令是第一类的情况下，由指令指定的第一基本寄存器装置中的寄存器的内容加上指令的地址部分以产生逻辑地址。另一方面，在指令是第二类的情况下，由与第一基本寄存器装置不同的指令指定的第二基本寄存器装置中的寄存器的内容与指令的地址部分并置，以产生一个逻辑地址。

35. 发明授权

US5422980A Inference processing method and apparatus 失效
标题翻译：推理处理方法和装置
公开(公告)号：US5422980A
公开(公告)日：1995-06-06
申请号：US145299
申请日：1993-11-03
申请人： Kenichi Kurosawa , Masaru Shimada , Tadaaki Bandoh , Toshihiko Nakano , Toshihiro Hayashi
发明人： Kenichi Kurosawa , Masaru Shimada , Tadaaki Bandoh , Toshihiko Nakano , Toshihiro Hayashi
IPC分类号： G06F9/44 , G06F9/45 , G06N5/04
CPC分类号： G06N5/046
摘要： A storage area for holding instantiation is provided together with a work area in order to rapidly generate a conflict set. When a condition of a rule is met, the instantiation of the rule is stored in the storage area in a form of data structure. The instantiation having an element whose attribute has been modified in an execution part of the rule is deleted from the conflict set.
摘要翻译：用于保持实例化的存储区域与工作区域一起提供，以便快速生成冲突集。当满足规则的条件时，规则的实例化以数据结构的形式存储在存储区域中。具有在规则的执行部分中其属性被修改的元素的实例被从冲突集中删除。

36. 发明授权

US5247649A Multi-processor system having a multi-port cache memory 失效
标题翻译：具有多端口高速缓冲存储器的多处理器系统
公开(公告)号：US5247649A
公开(公告)日：1993-09-21
申请号：US933892
申请日：1992-08-24
申请人： Tadaaki Bandoh
发明人： Tadaaki Bandoh
IPC分类号： G06F12/08
CPC分类号： G06F12/0853 , G06F12/084
摘要： A multi-port cache memory of multi-port memory structure is connected to and shared with a plurality of processors. The multi-port cache memory may have two sets of interface signal lines, for instruction fetch and for data read/write, to each processor. The multi-port cache memory may also be used only for data read/write. The system performance is further improved if a plurality of processors and a multi-port cache memory are fabricated on a single LSI chip.
摘要翻译：多端口存储器结构的多端口高速缓冲存储器连接到多个处理器并与多个处理器共享。多端口高速缓冲存储器可以具有两组接口信号线，用于指令提取和用于数据读/写的每个处理器。多端口缓存存储器也可以仅用于数据读/写。如果在单个LSI芯片上制造多个处理器和多端口高速缓冲存储器，则系统性能进一步提高。

37. 发明授权

US5003458A Suspended instruction restart processing system based on a checkpoint microprogram address 失效
标题翻译：基于检查点微程序地址的暂停指令重新启动处理系统
公开(公告)号：US5003458A
公开(公告)日：1991-03-26
申请号：US111618
申请日：1987-10-23
申请人： Shinichiro Yamaguchi , Hidekazu Matsumoto , Tadaaki Bandoh , Hirokazu Hirayama , Takayuki Morioka , Soichi Takaya , Yukio Kawamoto , Jushi Ide , Yoshihiro Miyazaki
发明人： Shinichiro Yamaguchi , Hidekazu Matsumoto , Tadaaki Bandoh , Hirokazu Hirayama , Takayuki Morioka , Soichi Takaya , Yukio Kawamoto , Jushi Ide , Yoshihiro Miyazaki
IPC分类号： G06F11/14
CPC分类号： G06F11/141
摘要： Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.
摘要翻译：在微程序控制数据处理装置中进行指令重新开始处理的方法和装置，其中，在指令暂停之后重启指令执行时，指令执行暂停时的数据处理装置的内部信息被保存在存储器中，之后暂停原因清除过程执行保存的内部信息被恢复。根据微程序的指定，存储与当前执行的微程序地址相关联的检查点地址。暂停之后，执行删除处理，指令的执行使用检查点地址重新开始。如果在暂停原因移除处理被执行之后没有存储检查点地址，则从主存储器的暂停指令的读取操作重新开始指令的执行。

38. 发明授权

US4839846A Apparatus for performing floating point arithmetic operations and rounding the result thereof 失效
标题翻译：用于执行浮点算术运算并舍入其结果的装置
公开(公告)号：US4839846A
公开(公告)日：1989-06-13
申请号：US838941
申请日：1986-03-12
申请人： Kenji Hirose , Tadaaki Bandoh , Hidekazu Matsumoto , Shinichiro Yamaguchi , Hirokazu Hirayama , Hiroaki Nakanishi
发明人： Kenji Hirose , Tadaaki Bandoh , Hidekazu Matsumoto , Shinichiro Yamaguchi , Hirokazu Hirayama , Hiroaki Nakanishi
IPC分类号： G06F7/00 , G06F7/38 , G06F7/485 , G06F7/50 , G06F7/508 , G06F7/76
CPC分类号： G06F7/485 , G06F7/49936 , G06F7/49957
摘要： An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as "1". The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).
摘要翻译：能够在浮点运算中高速进行圆形处理的运算部。提供一种用于在一个代表全局的输出中表示全部1的信号和表示四舍五入的信号，进位查找电路和用于产生圆形精度信号的电路的条件下检测溢出的电路。当溢出发生时，尾数产生为“1”。操作单元兼容电气和电子工程师协会（IEEE）推荐的单，双和扩展精度。

39. 发明授权

US4811269A Bit slice multiplication circuit 失效
标题翻译：位片倍增电路
公开(公告)号：US4811269A
公开(公告)日：1989-03-07
申请号：US916695
申请日：1986-10-08
申请人： Kenji Hirose , Tadaaki Bandoh , Hidekazu Matsumoto , Shinichiro Yamaguchi , Hirokazu Hirayama , Hiroaki Nakanishi
发明人： Kenji Hirose , Tadaaki Bandoh , Hidekazu Matsumoto , Shinichiro Yamaguchi , Hirokazu Hirayama , Hiroaki Nakanishi
IPC分类号： G06F7/487 , G06F7/506 , G06F7/508 , G06F7/52 , G06F7/527 , G06F7/53
CPC分类号： G06F7/5324 , G06F2207/3896
摘要： A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to the number of sliced multiplicands, and adding units provided in correspondence to the multiplying units and implementing summation for multiplication results from corresponding multiplying units while shifting the sliced portions of the multiplicand at each multiplying operation for sliced multipliers and multiplicands by the multiplying units, the multiplication result being obtained by summing all summation results produced by the adding units.
摘要翻译：一个用于切片乘法器的位片倍增电路，为分片乘法器产生乘积，并对乘积求和，得到乘法结果。该电路包括一个限幅单元，用于对被乘数进行分片，对应的乘法单元数目与分片被乘数的数目相对应，并且与乘法单元对应地设置的加法单位，并对相应的乘法单元进行相乘结果的求和，通过乘法单元在分片乘法器和被乘数的乘法运算中被乘数，乘法结果是通过将由加法单元产生的所有求和结果求和来获得的。

40. 发明授权

US4807113A Microprogrammed control data processing apparatus in which operand source and/or operand destination is determined independent of microprogram control 失效
标题翻译：微编程控制数据处理装置，其中确定操作数源和/或操作数目的地，独立于微程序控制
公开(公告)号：US4807113A
公开(公告)日：1989-02-21
申请号：US930532
申请日：1986-11-14
申请人： Hidekazu Matsumoto , Tadaaki Bandoh , Ryosei Hiraoka , Takayuki Morioka , Yoshihiro Miyazaki
发明人： Hidekazu Matsumoto , Tadaaki Bandoh , Ryosei Hiraoka , Takayuki Morioka , Yoshihiro Miyazaki
IPC分类号： G06F9/22 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/42 , G06F9/34 , G06F9/36
CPC分类号： G06F9/3016 , G06F9/3824
摘要： A microprogram controlled data processing apparatus executes multi-operand instructions in which one or more operand specifiers are provided for specifying the addressing for each operand independently from the operation code of the instruction. An instruction execution unit receives a top address of a microprogram from a decoding unit, a ready status signal and a signal from the decoding unit indicating whether a destination of an operand is in a general purpose register or in a memory unit, and writes an operand into a destination address of a register on the memory unit under control of a microprogram. Because the destination of the operand is indicated by the instruction decoding unit, it is not necessary to determine this information by microinstruction execution, with the result that execution of the instruction can be performed at high speed.
摘要翻译：微程序控制数据处理装置执行多操作指令，其中提供一个或多个操作数说明符，用于独立于指令的操作码指定每个操作数的寻址。指令执行单元从解码单元接收微程序的顶部地址，就绪状态信号和来自解码单元的指示操作数的目的地是否在通用寄存器中或存储单元中的信号，并且将操作数在微程序的控制下，转换到存储器单元上的寄存器的目的地地址。由于操作数的目的地由指令解码单元指示，所以不需要通过微指令执行来确定该信息，结果可以高速执行指令。

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