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    • 32. 发明授权
    • Liquid crystal display
    • 液晶显示器
    • US6049321A
    • 2000-04-11
    • US938333
    • 1997-09-25
    • Minoru Sasaki
    • Minoru Sasaki
    • G02F1/136G02F1/133G02F1/1368G09G3/36
    • G09G3/3688G09G3/3614G09G2310/027G09G2310/0297G09G2330/021
    • A liquid crystal display includes a matrix array of liquid crystal pixels, data lines formed along columns of the pixels, TFTs assigned to the pixels for causing the data lines to be electrically connected to the pixels of a selected row, and a data line driver which drives the data lines and has a first video bus for transmitting analog pixel signals of the positive polarity for the pixels of one of odd and even columns in a selected row, a second video bus for transmitting analog pixel signals of the negative polarity for the pixels of the other one of the odd and even columns in the selected row, sample-hold units each assigned to adjacent two of the data lines to simultaneously sample-hold the pixel signals on the first and second video buses, and a shift register circuit for enabling the operations of the sample-hold units sequentially. Particularly, each sample-hold unit has a first switch circuit for causing the first and second video buses to be connected to one of the adjacent two data lines and the other one of the adjacent two data lines, and a second switch circuit for causing the first and second video buses to be connected to the other one of the adjacent two data lines and the one of the adjacent two data lines, and the shift register circuit has a logic circuit for periodically switching between the first and second switch circuits of each sample-hold unit.
    • 液晶显示器包括液晶像素的矩阵阵列,沿着像素的列形成的数据线,分配给用于使数据线电连接到所选行的像素的像素的TFT以及数据线驱动器 驱动数据线,并且具有第一视频总线,用于传送所选行中的奇数和偶数列中的一个的像素的正极性的模拟像素信号;第二视频总线,用于发射用于像素的负极性的模拟像素信号 选择行中的奇数列和偶数列中的另一个的采样保持单元分别分配给相邻的两条数据线,以对第一和第二视频总线上的像素信号进行采样保持;以及移位寄存器电路, 使得采样保持单元的操作顺序。 特别地,每个采样保持单元具有第一开关电路,用于使第一和第二视频总线连接到相邻的两条数据线中的一条和相邻的两条数据线中的另一条数据线;以及第二开关电路, 第一和第二视频总线连接到相邻两条数据线中的另一条数据线和相邻的两条数据线之一,并且移位寄存器电路具有用于在每个样本的第一和第二开关电路之间周期性切换的逻辑电路 保持单位。
    • 34. 发明授权
    • Counter output detector circuit
    • 计数器输出检测电路
    • US4109141A
    • 1978-08-22
    • US830148
    • 1977-09-02
    • Minoru Sasaki
    • Minoru Sasaki
    • H03J7/18G06F7/02G06F7/04H03K19/21H03K21/40H03K21/10
    • G06F7/02H03K19/215H03K21/403
    • A counter and a memory device are included each of which includes n binary memory units. A coincident signal is outputted when the output data are coincident between the counter and the memory device. Each binary memory unit produces a binary output signal ("1" or "0") and its negated binary output signal ("1" or "0"). An exclusive OR circuit connected between the first stage memory units of the counter and the memory device. Between the corresponding memory units of the remaining each stage, and AND-OR circuit is provided being connected between a first and a second terminals. The AND-OR circuit is opened when the contents of two corresponding binary memory units are coincident. A first MOS transistor is connected between a common connection line of the first terminal and a power source. A second MOS transistor is connected between a common connection line of the second terminal and the ground. A coincident signal from the exclusive OR circuit makes the first MOS transistor conductive. The signal carried on the common connection line of the first terminal and the output signal of the exclusive OR circuit are applied to a NAND circuit. When the memory contents between the first stages are coincident and the AND-OR circuits are all opened, i.e. the contents of the counter and memory device are entirely coincident, the NAND circuit produces a coincident signal to indicate the coincidence between the output data of the counter and the memory device.
    • 38. 发明授权
    • Waste heat recovery system of heat source, with Rankine cycle
    • 热源余热回收系统,兰金循环
    • US07454910B2
    • 2008-11-25
    • US11053125
    • 2005-02-08
    • Shinichi HamadaMinoru SasakiAtsushi Inaba
    • Shinichi HamadaMinoru SasakiAtsushi Inaba
    • F01K23/10
    • F02G5/00F01K23/065Y02T10/166
    • A waste heat recovery system of an engine has a cooling water circuit and a Rankine cycle. Cooling water is circulated between the engine and a radiator in the cooling water circuit. The Rankine cycle has a heater and an expansion device. The heater performs heat exchange between the cooling water heated by the engine and an operation fluid so as to heat the operation fluid in the Rankine cycle. The expansion device expands the heated operation fluid, so as to generate driving power. The heater is arranged in a bypass circuit so as to be in parallel with the radiator with respect to the cooling water flow. Thus, waste heat of the cooling water heated by the engine can be effectively recovered without reducing a cooling capacity of the radiator.
    • 发动机的余热回收系统具有冷却水回路和兰金循环。 在冷却水回路中,发动机和散热器之间循环冷却水。 兰金循环有加热器和膨胀装置。 加热器在由发动机加热的冷却水和操作流体之间进行热交换,以加热兰金循环中的操作流体。 膨胀装置膨胀加热的操作流体,以产生驱动力。 加热器布置在旁路回路中,以便相对于冷却水流与散热器平行。 因此,可以有效地回收由发动机加热的冷却水的废热,而不降低散热器的冷却能力。