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31. 发明授权

US07349249B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07349249B2
公开(公告)日：2008-03-25
申请号：US11389083
申请日：2006-03-27
申请人： Mitsuaki Honma , Noboru Shibata , Kazunori Kanebako
发明人： Mitsuaki Honma , Noboru Shibata , Kazunori Kanebako
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5641 , G11C2211/5646
摘要： A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell storing data defined by threshold voltage thereof, wherein the memory cell array includes first and second areas; the first area stores multi-value data written with plural write steps; and the second area stores binary data defined by first and second logic states, threshold levels of which are controlled through the plural write steps adapted to the multi-value data write.
摘要翻译：半导体存储器件包括其中布置有存储器单元的存储单元阵列，每个存储器单元存储由其阈值电压定义的数据，其中存储单元阵列包括第一和第二区域; 第一区域存储用多个写入步骤写入的多值数据; 并且第二区域存储由第一和第二逻辑状态定义的二进制数据，其阈值级别通过适于多值数据写入的多个写入步骤来控制。

32. 发明授权

US07342825B2 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells 有权
公开(公告)号：US07342825B2
公开(公告)日：2008-03-11
申请号：US11690674
申请日：2007-03-23
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

33. 发明授权

US07315471B2 Semiconductor memory device for storing multivalued data 有权
标题翻译：用于存储多值数据的半导体存储器件
公开(公告)号：US07315471B2
公开(公告)日：2008-01-01
申请号：US11469279
申请日：2006-08-31
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.
摘要翻译：数据存储电路以一一对应的方式连接到位线。写电路将第一页上的数据写入由字线同时选择的多个第一存储单元。此后，写电路将第二页上的数据写入多个第一存储单元。然后，写入电路将第一和第二页面上的数据写入与位线方向相邻的第一存储单元的第二存储单元。

34. 发明申请

US20070280017A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070280017A1
公开(公告)日：2007-12-06
申请号：US11772271
申请日：2007-07-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

35. 发明授权

US07295469B2 Nonvolatile semiconductor memory device with a ROM block settable in a write/erase inhibit mode 有权
标题翻译：具有可设置为写/擦除禁止模式的ROM块的非易失性半导体存储器件
公开(公告)号：US07295469B2
公开(公告)日：2007-11-13
申请号：US11530340
申请日：2006-09-08
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/22
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

36. 发明申请

US20070253272A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF EXECUTING HIGH-SPEED READ 有权
标题翻译：可执行高速读取的半导体存储器件
公开(公告)号：US20070253272A1
公开(公告)日：2007-11-01
申请号：US11737413
申请日：2007-04-19
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C8/00
CPC分类号： G11C16/12 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/565
摘要： A plurality of memory cells are arranged in a memory cell array. The plurality of memory cells are connected to a plurality of word lines and a plurality of bit lines. A plurality of source lines are disposed along the plurality of bit lines. The plurality of source lines are connected respectively to sources of the plurality of memory cells at a time of data read.
摘要翻译：多个存储单元布置在存储单元阵列中。多个存储单元连接到多个字线和多个位线。多条源极线沿多条位线配置。多个源极线在数据读取时分别连接到多个存储单元的源极。

37. 发明授权

US07074158B2 Shift control apparatus of automatic transmission of motor vehicle 有权
公开(公告)号：US07074158B2
公开(公告)日：2006-07-11
申请号：US10821960
申请日：2004-04-12
申请人： Kazuyuki Watanabe , Toshimitsu Sato , Atsushi Ayabe , Shinji Kato , Naoyuki Sakamoto , Hiromichi Kimura , Noboru Shibata , Mitsuhiro Nakamura , Hideaki Ogasawara
发明人： Kazuyuki Watanabe , Toshimitsu Sato , Atsushi Ayabe , Shinji Kato , Naoyuki Sakamoto , Hiromichi Kimura , Noboru Shibata , Mitsuhiro Nakamura , Hideaki Ogasawara
IPC分类号： F16H61/04
CPC分类号： B60W10/06 , B60W10/04 , B60W10/11 , B60W10/115 , B60W30/1819 , B60W30/19 , B60W2520/10 , B60W2540/12 , B60W2710/0644 , B60W2710/0661 , F16H61/061 , F16H61/686 , F16H63/502 , F16H2059/467 , F16H2061/0087 , F16H2061/0496 , F16H2200/0047 , F16H2306/54 , Y02T10/76 , Y10T477/6333 , Y10T477/675 , Y10T477/679 , Y10T477/693636 , Y10T477/69366 , Y10T477/69367 , Y10T477/693958
摘要： A shift control apparatus of an automatic transmission of a motor vehicle to which torque is transmitted from an engine via a fluid coupling device is provided. In the automatic transmission including a plurality of hydraulically operated friction elements, a clutch-to-clutch downshift is carried out during coasting of the vehicle by releasing one of the friction elements and engaging another friction element. A controller of the shift control apparatus detects a difference between input and output rotation speeds of the fluid coupling device, and increases an engine speed by a controlled amount based on the difference between the input and output rotation speeds when the clutch-to-clutch downshift is carried out during coasting of the vehicle, so that the vehicle is brought into a minimal driving state in which the engine speed is slightly higher than the output rotation speed of the fluid coupling device.

38. 发明申请

US20060146610A1 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells 有权
公开(公告)号：US20060146610A1
公开(公告)日：2006-07-06
申请号：US11336944
申请日：2006-01-23
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

39. 发明申请

US20060092708A1 Semiconductor memory device and electric device with the same 有权
标题翻译：半导体存储器件和电器件相同
公开(公告)号：US20060092708A1
公开(公告)日：2006-05-04
申请号：US11305193
申请日：2005-12-19
申请人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
发明人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/06
CPC分类号： G11C16/3468
摘要： A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for the first area of the first cell array block and a second area of a second cell array block are simultaneously executed, while the busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of the first area held in the sense amplifier circuits to the chip external, and in a second read cycle selecting the second area in the second cell array block, after the busy signal generation circuit has output a dummy busy signal shorter in time length than the true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of the second area held in the sense amplifier circuits to the chip external.
摘要翻译：半导体存储器件包括：多个单元阵列块，每个单元阵列块中布置有多个存储单元; 用于选择单元阵列块中的存储单元的地址解码电路; 用于读取单元阵列块的单元数据的读出放大器电路; 以及用于向芯片外部产生忙信号的忙信号产生电路，其中在第一读周期中选择第一单元阵列块中的第一区，对第一单元阵列块的第一区进行单元数据读操作，同时执行第二单元阵列块的区域，而忙信号产生电路产生真正的忙信号，然后执行读数据输出操作，以将保持在读出放大器电路中的第一区域的读出数据输出到芯片外部，并且在第二读取周期中选择第二单元阵列块中的第二区域，在忙信号产生电路在不执行单元数据读取操作的情况下输出比真实忙信号更短的时间长度的虚拟忙信号，读取执行数据输出操作，以将保持在读出放大器电路中的第二区域的读出数据输出到芯片外部。

40. 发明授权

US06977845B2 Semiconductor memory device and electric device with the same 有权
公开(公告)号：US06977845B2
公开(公告)日：2005-12-20
申请号：US10856986
申请日：2004-06-01
申请人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
发明人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/26 , G11C16/34 , H01L27/00
CPC分类号： G11C16/3468
摘要： A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for the first area of the first cell array block and a second area of a second cell array block are simultaneously executed, while the busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of the first area held in the sense amplifier circuits to the chip external, and in a second read cycle selecting the second area in the second cell array block, after the busy signal generation circuit has output a dummy busy signal shorter in time length than the true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of the second area held in the sense amplifier circuits to the chip external.

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