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31. 发明授权

US08501550B2 Method of fabricating gate and method of manufacturing semiconductor device using the same 有权
标题翻译：制造栅极的方法和使用其制造半导体器件的方法
公开(公告)号：US08501550B2
公开(公告)日：2013-08-06
申请号：US13238330
申请日：2011-09-21
申请人： Jong-Pil Kim , Young-Goan Jang , Dong-Won Kim , Hag-Ju Cho
发明人： Jong-Pil Kim , Young-Goan Jang , Dong-Won Kim , Hag-Ju Cho
IPC分类号： H01L21/335 , H01L21/8232
CPC分类号： H01L21/28008 , H01L21/28123 , H01L21/76 , H01L21/76232 , H01L21/823437 , H01L21/823481 , H01L29/165 , H01L29/49 , H01L29/66545 , H01L29/6656 , H01L29/7848
摘要： A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.
摘要翻译：制造栅极的方法包括在基板的基本上整个表面上依次形成绝缘层和导电层。衬底在其中具有器件隔离层，器件隔离层的顶表面高于衬底的顶表面。该方法包括通过图案化绝缘层和导电层来平坦化导电层的顶表面并形成栅电极。

32. 发明申请

US20090134466A1 DUAL WORK FUNCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：双功能半导体器件及其制造方法
公开(公告)号：US20090134466A1
公开(公告)日：2009-05-28
申请号：US12258222
申请日：2008-10-24
申请人： Hag-Ju Cho , Shih-Hsun Chang
发明人： Hag-Ju Cho , Shih-Hsun Chang
IPC分类号： H01L25/03 , H01L21/4763
CPC分类号： H01L21/823462 , H01L21/82345 , H01L21/823842 , H01L21/823857 , H01L27/088 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing dual work function devices starting from a single metal electrode and the device resulting therefrom are disclosed. In one aspect, the method includes a single-metal-single-dielectric (SMSD) CMOS integration scheme. A single dielectric stack comprising a gate dielectric layer and a dielectric capping layer and one metal layer overlying the dielectric stack are first deposited, forming a metal-dielectric interface. Upon forming the dielectric stack and the metal layer, at least part of the dielectric capping layer is selectively modified by adding work function tuning elements, the part being adjacent to the metal-dielectric interface.
摘要翻译：公开了从单个金属电极开始制造双功能功能器件的方法以及由此产生的器件。一方面，该方法包括单金属单电介质（SMSD）CMOS集成方案。首先沉积包括栅极电介质层和电介质覆盖层和覆盖在电介质叠层上的一个金属层的单个电介质堆叠，形成金属 - 电介质界面。在形成电介质堆叠和金属层时，通过加入功函数调谐元件来选择性地修改介电顶盖层的至少一部分，该部分与金属 - 电介质界面相邻。

33. 发明授权

US6096592A Methods of forming integrated circuit capacitors having plasma treated regions therein 失效
标题翻译：形成其中具有等离子体处理区域的集成电路电容器的方法
公开(公告)号：US6096592A
公开(公告)日：2000-08-01
申请号：US22311
申请日：1998-02-11
申请人： Hag-Ju Cho
发明人： Hag-Ju Cho
IPC分类号： H01L27/04 , H01L21/02 , H01L21/314 , H01L21/822 , H01L21/8242 , H01L27/08 , H01L27/108 , H01L21/8234
CPC分类号： H01L28/55 , H01L27/0805
摘要： Methods of forming integrated circuit capacitors include the steps of forming a capacitor comprising first and second electrodes and a dielectric layer between the first and second electrodes, on a substrate. A step is then performed to expose at least one of the dielectric layer and the second electrode to an ECR plasma for a duration of sufficient length to improve charge leakage characteristics of the integrated circuit capacitor. The dielectric layer may comprise STO, BST, PZT, SBT PLZT and BTO, for example. This exposing step may include the step of selectively exposing the second electrode, but not the ferroelectric dielectric layer, to the ECR plasma. The exposing step also preferably includes simultaneously maintaining the substrate at a temperature below about 700.degree. C.
摘要翻译：形成集成电路电容器的方法包括在基板上形成包括第一和第二电极的电容器以及第一和第二电极之间的电介质层的步骤。然后执行步骤以将电介质层和第二电极中的至少一个暴露于ECR等离子体持续足够的长度以改善集成电路电容器的电荷泄漏特性。介电层可以包括例如STO，BST，PZT，SBT PLZT和BTO。该曝光步骤可以包括将第二电极而不是铁电电介质层选择性地暴露于ECR等离子体的步骤。曝光步骤还优选地包括同时将基底保持在低于约700℃的温度。

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