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31. 发明授权

US11984261B2 Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device 有权
公开(公告)号：US11984261B2
公开(公告)日：2024-05-14
申请号：US17411416
申请日：2021-08-25
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Anderson Lin , Chun-Ren Cheng , Chi-Yuan Shih , Shih-Fen Huang , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Fu-Chun Huang , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
IPC分类号： H01G4/012 , H01G4/12 , H01G4/228 , H01L21/311 , H01L21/3213 , H01L41/047 , H01L41/083 , H01L41/113 , H01L49/02 , H10N30/30 , H10N30/50 , H10N30/87
CPC分类号： H01G4/012 , H01G4/12 , H01G4/228 , H01L21/31111 , H01L21/32139 , H01L28/60 , H10N30/302 , H10N30/501 , H10N30/508 , H10N30/872
摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

32. 发明公开

US20240069275A1 WAVELENGTH TUNING IN SILICON PHOTONICS 审中-公开
公开(公告)号：US20240069275A1
公开(公告)日：2024-02-29
申请号：US18298574
申请日：2023-04-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Beih-Tzun Lin , Chi-Yuan Shih , Feng Yuan , Shih-Fen Huang
IPC分类号： G02B6/12 , G02B6/13
CPC分类号： G02B6/12002 , G02B6/12004 , G02B6/13 , G02B2006/12061
摘要： A method of wavelength tuning in a silicon photonics circuit includes receiving a bus waveguide, a ring resonator optically coupled to the bus waveguide, and a dielectric layer over the bus waveguide and over the ring resonator. The method further includes performing a first heat process at a first temperature to heat up the dielectric layer, where the first heat process shifts an initial resonance wavelength of the ring resonator to a first resonance wavelength shorter than the initial resonance wavelength. The first heat process permanently shifts the initial resonance wavelength to the first resonance wavelength, the first resonance wavelength being a wavelength when no heat is being applied to the ring resonator.

33. 发明授权

US11856862B2 Fatigue-free bipolar loop treatment to reduce imprint effect in piezoelectric device 有权
公开(公告)号：US11856862B2
公开(公告)日：2023-12-26
申请号：US17874446
申请日：2022-07-27
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chi-Yuan Shih , Shih-Fen Huang , You-Ru Lin , Yan-Jie Liao
IPC分类号： H10N39/00 , H10N30/074 , H10N30/20
CPC分类号： H10N39/00 , H10N30/074 , H10N30/206
摘要： In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.

34. 发明公开

US20230302494A1 HYBRID ULTRASONIC TRANSDUCER SYSTEM 审中-公开
公开(公告)号：US20230302494A1
公开(公告)日：2023-09-28
申请号：US17832937
申请日：2022-06-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Hui Lin , Yi-Hsien Chang , Chun-Ren Cheng , Fu-Chun Huang , Yi Heng Tsai , Shih-Fen Huang , Chao-Hung Chu , Po-Chen Yeh
IPC分类号： B06B1/02 , B06B1/06
CPC分类号： B06B1/0292 , B06B1/0622
摘要： The present disclosure relates to an integrated chip structure. The integrated chip structure includes a dielectric stack disposed on a substrate. The integrated chip structure further includes one or more piezoelectric ultrasonic transducers (PMUTs) and one or more capacitive ultrasonic transducers (CMUTs). The one or more PMUTs include a piezoelectric stack disposed within the dielectric stack over one or more PMUT cavities. The one or more CMUTs include electrodes disposed within the dielectric stack and separated by one or more CMUT cavities. An isolation chamber is arranged within the dielectric stack laterally between the one or more PMUTs and the one or more CMUTs. The isolation chamber vertically extends past at least a part of both the one or more PMUTs and the one or more CMUTs.

35. 发明授权

US11757034B2 High voltage device 有权
公开(公告)号：US11757034B2
公开(公告)日：2023-09-12
申请号：US17731159
申请日：2022-04-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Hung-Sen Wang , Yun-Ta Tsai , Ruey-Hsin Liu , Shih-Fen Huang , Ho-Chun Liou
IPC分类号： H01L29/78 , H01L27/06 , H01L29/06 , H01L29/66 , H01L29/423
CPC分类号： H01L29/7816 , H01L27/0617 , H01L29/0653 , H01L29/42356 , H01L29/66681
摘要： A high-voltage device includes a first frame-like isolation and a second frame-like isolation separated from each other, a first frame-like gate structure covering the first frame-like isolation, a second frame-like gate structure covering the second frame-like isolation, a first drain region enclosed by the first frame-like isolation, a second drain region enclosed by the second frame-like isolation, a first frame-like source region surrounding the first frame-like gate structure, a second frame-like source region surrounding the second frame-like gate structure, a first doped region surrounding the first and second frame-like gate structures, and a second doped region disposed between the first and second frame-like gate structures. The first and second drain regions, and the first and second frame-like source regions include a first conductivity type. The first and the second doped region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

36. 发明申请

US20220367564A1 FATIGUE-FREE BIPOLAR LOOP TREATMENT TO REDUCE IMPRINT EFFECT IN PIEZOELECTRIC DEVICE 有权
公开(公告)号：US20220367564A1
公开(公告)日：2022-11-17
申请号：US17874446
申请日：2022-07-27
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chi-Yuan Shih , Shih-Fen Huang , You-Ru Lin , Yan-Jie Liao
IPC分类号： H01L27/20 , H01L41/314 , H01L41/09
摘要： In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.

37. 发明授权

US10164005B2 Deep trench capacitor with a filled trench and a doped region serving as a capacitor electrode 有权
公开(公告)号：US10164005B2
公开(公告)日：2018-12-25
申请号：US15072906
申请日：2016-03-17
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Felix Ying-Kit Tsui , Shih-Fen Huang
IPC分类号： H01L29/00 , H01L49/02
摘要： The present disclosure provides a semiconductor structure which comprises a semiconductive substrate and a doped region in the semiconductive substrate. The doped region has a conductivity type opposite to the semiconductive substrate. The semiconductor structure also includes a capacitor in the doped region where the capacitor comprises a plurality of electrodes and the plurality of electrodes are insulated with one another. The semiconductor structure further includes a plug in the capacitor and surrounded by the plurality of electrodes.

38. 发明申请

US20170067890A1 On-Chip Disease Diagnostic Platform for Dual-Gate Ion Sensitive Field Effect Transistor 审中-公开
标题翻译：双栅离子敏感场效应晶体管片上疾病诊断平台
公开(公告)号：US20170067890A1
公开(公告)日：2017-03-09
申请号：US15356503
申请日：2016-11-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Hui Lin , Chun-Ren Cheng , Yi-Hsien Chang , Shih-Fen Huang
IPC分类号： G01N33/543 , G01N27/414
CPC分类号： G01N33/54373 , G01N27/4145 , G01N27/4148 , H01L51/0093 , H01L51/0512
摘要： Dual-gate ion-sensitive field effect transistor (ISFET) and methods implementing the dual-gate ISFETs for disease diagnostics are disclosed herein. An exemplary method includes providing a biological sample to a dual-gate ISFET. The dual-gate ISFET includes a fluidic gate structure and a gate structure, where the fluidic gate structure and the gate structure are disposed over opposite surfaces of a device substrate. The method further includes generating enzymatic reactions from enzyme-modified detection mechanisms. The enzyme-modified detection mechanisms release ions into an electrolyte solution of the fluidic gate structure. The method further includes biasing the fluidic gate structure and the gate structure to generate an electrical signal as a sensing layer of the fluidic gate structure reacts with the ions. The electrical signal indicates an ion concentration in the electrolyte solution that correlates with a presence or a quantity of target analytes in the biological sample.
摘要翻译：本文公开了双栅离子敏感场效应晶体管（ISFET）和实现用于疾病诊断的双栅极ISFET的方法。一种示例性方法包括向双栅极ISFET提供生物样品。双栅极ISFET包括流体栅极结构和栅极结构，其中流体栅极结构和栅极结构设置在器件衬底的相对表面上。该方法还包括从酶修饰的检测机制产生酶反应。酶修饰的检测机制将离子释放到流体门结构的电解质溶液中。该方法还包括偏压流体栅极结构和栅极结构以在流体栅极结构的感测层与离子反应时产生电信号。电信号表示与生物样品中目标分析物的存在或数量相关的电解质溶液中的离子浓度。

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